Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style V Foroutan, MR Taheri, K Navi, AA Mazreah Integration 47 (1), 48-61, 2014 | 113 | 2014 |
An energy and area efficient 4: 2 compressor based on FinFETs A Arasteh, MH Moaiyeri, MR Taheri, K Navi, N Bagherzadeh Integration 60, 224-231, 2018 | 53 | 2018 |
A novel majority based imprecise 4: 2 compressor with respect to the current and future VLSI industry MR Taheri, A Arasteh, S Mohammadyan, A Panahi, K Navi Microprocessors and Microsystems 73, 102962, 2020 | 40 | 2020 |
Novel CNFET Ternary Circuit Techniques for High-performance and Energy-efficient Design S Tabrizchi, MR Taheri, K Navi, N Bagherzadeh IET Circuits Devices & Systems, 2018 | 40 | 2018 |
High speed reverse converter for new five-moduli set {2n, 22n+ 1-1, 2n/2-1, 2n/2+ 1, 2n+ 1} M Esmaeildoust, K Navi, MR Taheri IEICE Electronics Express 7 (3), 118-125, 2010 | 19 | 2010 |
Rnsim: Efficient deep neural network accelerator using residue number systems A Roohi, MR Taheri, S Angizi, D Fan 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 18 | 2021 |
Toward Efficient Implementation of Basic Balanced Ternary Arithmetic Operations in CNFET Technology M Toulabinejad, MR Taheri, K Navi, N Bagherzadeh Microelectronics Journal, 2019 | 17 | 2019 |
Comparative analysis of adiabatic full adder cells in CNFET technology MR Taheri, R Akbar, F Safaei, MH Moaiyeri Engineering Science and Technology, an International Journal 19 (4), 2119-2128, 2016 | 17 | 2016 |
Efficient RNS to binary converters for the new 4-moduli set {2n, 2n+ 1-1, 2n-1, 2n-1-1} M Esmaeildoust, K Navi, MR Taheri, AS Molahosseini, S Khodambashi IEICE Electronics Express 9 (1), 1-7, 2012 | 10 | 2012 |
Spin-based Imprecise 4-2 Compressor for Energy-Efficient Multipliers MR Taheri, F Sharifi, MA Shafiabadi, H Mahmoodi, K Navi SPIN, 2019 | 8 | 2019 |
Towards Approximate Computing with Quantum-Dot Cellular Automata Z Rouhani, S Angizi, MR Taheri, K Navi, N Bagherzadeh Journal of Low Power Electronics 13 (1), 29–35, 2017 | 8 | 2017 |
A high speed residue-to-binary converter for balanced 4-moduli set MR Taheri, N Shafiee, M Esmaeildoust, Z Amirjamshidi, ... Journal of Computing and Security 2 (1), 43-54, 2015 | 8 | 2015 |
Efficient Reverse Converter Design for Five Moduli Set {2n, 22n+1−1, 2n/2−1, 2n/2+1, 2n+1} MR Taheri, E Khani, M Esmaeildoust, K Navi Journal of Computations & Modelling 2 (1), 93-108, 2012 | 8 | 2012 |
Processing-in-memory acceleration of mac-based applications using residue number system: A comparative study S Angizi, A Roohi, MR Taheri, D Fan Proceedings of the 2021 Great Lakes Symposium on VLSI, 265-270, 2021 | 6 | 2021 |
Efficient incorporation of the rns datapath in reverse converter MR Taheri, AS Molahosseini, K Navi IEEE Transactions on Circuits and Systems II: Express Briefs 68 (4), 1388-1392, 2020 | 5 | 2020 |
Efficient programmable power‐of‐two scaler for the three‐moduli set {2n+p, 2n − 1, 2n+1 − 1} MR Taheri, K Navi, A Sabbagh Molahosseini ETRI Journal 42 (4), 596-607, 2020 | 5 | 2020 |
Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing E Faghih, MR Taheri, K Navi, N Bagherzadeh Sustainable Computing: Informatics and Systems 40, 100908, 2023 | 4 | 2023 |
High Speed Reverse Converter for High Dynamic Range Moduli Set MR Taheri, A Pirhoseinlo, M Esmaeildoust, M Esmaeildoust, K Navi International Journal of Advances in Engineering & Technology 3 (2), 26-37, 2012 | 3 | 2012 |
Energy-Efficient approximate compressor design for error-resilient digital signal processing A Avan, MR Taheri, MH Moaiyeri, K Navi International Journal of Electronics 110 (9), 1555-1577, 2023 | 2 | 2023 |
ReFACE: efficient design methodology for acceleration of digital filter implementations A Roohi, S Angizi, P Navaeilavasani, MR Taheri 2022 23rd International Symposium on Quality Electronic Design (ISQED), 1-6, 2022 | 1 | 2022 |