| A 480 mW 2.6 GS/s 10b time-interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm CMOS K Doris, E Janssen, C Nani, A Zanikopoulos, G Van der Weide IEEE Journal of Solid-State Circuits 46 (12), 2821-2833, 2011 | 151 | 2011 |
| A 480 mW 2.6 GS/s 10b time-interleaved ADC with 48.5 dB SNDR up to Nyquist in 65 nm CMOS K Doris, E Janssen, C Nani, A Zanikopoulos, G Van der Weide IEEE Journal of Solid-State Circuits 46 (12), 2821-2833, 2011 | 151 | 2011 |
| A 14 bit 200 MS/s DAC With SFDR> 78 dBc, IM3<-83 dBc and NSD<-163 dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping Y Tang, J Briaire, K Doris, R van Veldhoven, PCW van Beek, HJA Hegt, ... IEEE Journal of Solid-State Circuits 46 (6), 1371-1381, 2011 | 130 | 2011 |
| A 14b 200MS/s DAC with SFDR> 78dBc, IM3 Y Tang, J Briaire, K Doris, RHM van Veldhoven, PCW van Beek, JA Hegt, ... | 130* | 2010 |
| An 11b 3.6 GS/s time-interleaved SAR ADC in 65nm CMOS E Janssen, K Doris, A Zanikopoulos, A Murroni, G Van der Weide, Y Lin, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 117 | 2013 |
| A 14b 35MS/s SAR ADC Achieving 75dB SNDR and 99dB SFDR with Loop-Embedded Input Buffer in 40nm CMOS M Krämer, E Janssen, K Doris, B Murmann International Solid State Circuits Conference, 2015 | 109 | 2015 |
| A 480mW 2.6 GS/s 10b 65nm CMOS time-interleaved ADC with 48.5 dB SNDR up to Nyquist K Doris, E Janssen, C Nani, A Zanikopoulos, G Van der Weide 2011 IEEE International Solid-State Circuits Conference, 180-182, 2011 | 89 | 2011 |
| Wide-bandwidth high dynamic range D/A converters K Doris, AHM van Roermund, DMW Leenaerts Springer, 2006 | 70 | 2006 |
| Mismatch-based timing errors in current steering DACs K Doris, A van Roermund, D Leenaerts Circuits and Systems, 2003. ISCAS'03. Proceedings of the 2003 International …, 2003 | 45 | 2003 |
| A general analysis on the timing jitter in D/A converters K Doris, A van Roermund, D Leenaerts Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on 1, I …, 2002 | 43 | 2002 |
| A general analysis on the timing jitter in D/A converters K Doris, A van Roermund, D Leenaerts Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on 1, I …, 2002 | 43 | 2002 |
| High-speed D/A converters: from analysis and synthesis concepts to IC implementation K Doris Eindhoven University of Technology, Faculty of Electrical Engineering, 2004 | 37 | 2004 |
| Power-efficient high-speed parallel-sampling ADCs for broadband multi-carrier systems Y Lin, H Hegt, K Doris, AHM van Roermund Springer International Publishing, 2015 | 34* | 2015 |
| A 14 bit, 30 MS/s, 38 mW SAR ADC Using Noise Filter Gear Shifting M Kramer, E Janssen, K Doris, B Murmann IEEE, 0 | 27 | |
| A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS Y Lin, K Doris, H Hegt, A van Roermund 2012 IEEE International Symposium on Circuits and Systems, 2737-2740, 2012 | 25 | 2012 |
| Multi-channel receiver architecture and reception method K Doris, E Janssen US Patent 8,086,197, 2011 | 25 | 2011 |
| Data processing device comprising ADC unit K Doris US Patent 7,944,383, 2011 | 21 | 2011 |
| Statistical analysis of mapping technique for timing error correction in current-steering DACs Y Tang, H Hegt, A van Roermund, K Doris, J Briaire 2007 IEEE International Symposium on Circuits and Systems, 1225-1228, 2007 | 21 | 2007 |
| D/A conversion: amplitude and time error mapping optimization K Doris, C Lin, D Leenaerts, A van Roermund Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE …, 2001 | 21 | 2001 |
| An 11b pipeline ADC with parallel-sampling technique for converting multi-carrier signals Y Lin, K Doris, H Hegt, AHM van Roermund IEEE Transactions on Circuits and Systems I: Regular Papers 59 (5), 906-914, 2012 | 19 | 2012 |
