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Shreyas Kolala Venkataramanaiah
Shreyas Kolala Venkataramanaiah
Research associate, Arizona State Univeristy
在 asu.edu 的电子邮件经过验证 - 首页
标题
引用次数
引用次数
年份
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations
S Yin, SK Venkataramanaiah, GK Chen, R Krishnamurthy, Y Cao, ...
2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-5, 2017
752017
FixyNN: Efficient hardware for mobile computer vision via transfer learning
PN Whatmough, C Zhou, P Hansen, SK Venkataramanaiah, J Seo, ...
arXiv preprint arXiv:1902.11128, 2019
73*2019
Automatic compiler based FPGA accelerator for CNN training
SK Venkataramanaiah, Y Ma, S Yin, E Nurvithadhi, A Dasu, Y Cao, J Seo
2019 29th International Conference on Field Programmable Logic and …, 2019
572019
FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory
SK Venkataramanaiah, HS Suh, S Yin, E Nurvitadhi, A Dasu, Y Cao, ...
Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020
292020
Fixyfpga: Efficient fpga accelerator for deep neural networks with high element-wise sparsity and without external memory access
J Meng, SK Venkataramanaiah, C Zhou, P Hansen, P Whatmough, J Seo
2021 31st International Conference on Field-Programmable Logic and …, 2021
282021
Deep neural network training accelerator designs in ASIC and FPGA
SK Venkataramanaiah, S Yin, Y Cao, JS Seo
2020 International SoC Design Conference (ISOCC), 21-22, 2020
182020
Minimizing area and energy of deep learning hardware design using collective low precision and structured compression
S Yin, G Srivastava, SK Venkataramanaiah, C Chakrabarti, V Berisha, ...
2017 51st Asilomar Conference on Signals, Systems, and Computers, 1907-1911, 2017
132017
Algorithm-hardware co-optimization for energy-efficient drone detection on resource-constrained fpga
HS Suh, J Meng, T Nguyen, V Kumar, Y Cao, JS Seo
ACM Transactions on Reconfigurable Technology and Systems 16 (2), 1-25, 2023
102023
Efficient and Modularized Training on FPGA for Real-time Applications.
SK Venkataramanaiah, X Du, Z Li, S Yin, Y Cao, J Seo
IJCAI, 5237-5239, 2020
42020
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification
SK Venkataramanaiah, J Meng, HS Suh, I Yeo, J Saikia, SK Cherupally, ...
ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC), 89-92, 2022
32022
FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro
J Saikia, A Sridharan, I Yeo, S Venkataramanaiah, D Fan, JS Seo
ESSCIRC 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC …, 2023
22023
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity
SK Venkataramanaiah, J Meng, HS Suh, I Yeo, J Saikia, SK Cherupally, ...
IEEE Journal of Solid-State Circuits 58 (7), 1885-1897, 2023
22023
Online knowledge acquisition with the selective inherited model
X Du, SK Venkataramanaiah, Z Li, J Seo, F Liu, Y Cao
2020 International Joint Conference on Neural Networks (IJCNN), 1-7, 2020
22020
Efficient continual learning at the edge with progressive segmented training
X Du, SK Venkataramanaiah, Z Li, HS Suh, S Yin, G Krishnan, F Liu, ...
Neuromorphic Computing and Engineering 2 (4), 044006, 2022
12022
Energy Efficient ASIC/FPGA Neural Network Accelerators
SK venkataramanaiah
https://keep.lib.asu.edu/items/171744, 2022
2022
Energy Efficient Hardware Design of Neural Networks
SK Venkataramanaiah
Arizona State University, 2018
2018
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