| A built-in self-repair design for RAMs with 2-D redundancy JF Li, JC Yeh, RF Huang, CW Wu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (6), 742-745, 2005 | 133 | 2005 |
| A built-in self-repair scheme for semiconductor memories with 2-D redundancy JF Li, JC Yeh, RF Huang, CW Wu, PY Tsai, A Hsu, E Chow International Test Conference, 2003. Proceedings. ITC 2003., 393-393, 2003 | 91 | 2003 |
| Flash memory built-in self-test using march-like algorithms JC Yeh, CF Wu, KL Cheng, YF Chou, CT Huang, CW Wu Proceedings First IEEE International Workshop on Electronic Design, Test and …, 2002 | 73 | 2002 |
| A simulator for evaluating redundancy analysis algorithms of repairable embedded memories RF Huang, JF Li, JC Yeh, CW Wu Proceedings of the 2002 IEEE International Workshop on Memory Technology …, 2002 | 60 | 2002 |
| RAMSES-FT: A fault simulator for flash memory testing and diagnostics KL Cheng, JC Yeh, CW Wang, CT Huang, CW Wu Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 281-286, 2002 | 55 | 2002 |
| Flash memory testing and built-in self-diagnosis with march-like test algorithms JC Yeh, KL Cheng, YF Chou, CW Wu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 54 | 2007 |
| Diagonal test and diagnostic schemes for flash memories SK Chiu, JC Yeh, CT Huang, CW Wu Proceedings. International Test Conference, 37-46, 2002 | 43 | 2002 |
| Diagonal testing method for flash memories SK Chiu, JC Yeh, KL Cheng, CT Huang, CW Wu US Patent 7,065,689, 2006 | 42 | 2006 |
| Raisin: Redundancy analysis algorithm simulation RF Huang, JC Yeh, JF Li, CW Wu IEEE Design & Test of Computers 24 (4), 386-396, 2007 | 37 | 2007 |
| PowerDepot: Integrating IP-based power modeling with ESL power analysis for multi-core SoC designs CW Hsu, JL Liao, SC Fang, CC Weng, SY Huang, WT Hsieh, JC Yeh Proceedings of the 48th Design Automation Conference, 47-52, 2011 | 33 | 2011 |
| Automatic generation of memory built-in self-test cores for system-on-chip KL Cheng, CM Hsueh, JR Huang, JC Yeh, CT Huang, CW Wu Proceedings 10th Asian Test Symposium, 91-96, 2001 | 30 | 2001 |
| A network security processor design based on an integrated SOC design and test platform CH Wang, CY Lo, MS Lee, JC Yeh, CT Huang, CW Wu, SY Huang Proceedings of the 43rd Annual Design Automation Conference, 490-495, 2006 | 29 | 2006 |
| Techniques for accessing a dynamic random access memory array A Schaefer, JC Yeh, PW Luo US Patent 9,135,982, 2015 | 27 | 2015 |
| Full system simulation and verification framework JW Lin, CC Wang, CY Chang, CH Chen, KJ Lee, YH Chu, JC Yeh, ... 2009 Fifth International Conference on Information Assurance and Security 1 …, 2009 | 21 | 2009 |
| An accurate system architecture refinement methodology with mixed abstraction-level virtual platform ZM Hsu, JC Yeh, IY Chuang 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 18 | 2010 |
| System performance analyses on PAC Duo ESL virtual platform ZM Hsu, IY Chuang, WC Su, JC Yeh, JK Yang, SY Tseng 2009 Fifth International Conference on Intelligent Information Hiding and …, 2009 | 18 | 2009 |
| An enhanced EDAC methodology for low power PSRAM PY Chen, YT Yeh, CH Chen, JC Yeh, CW Wu, J Lee, Y Lin 2006 IEEE International Test Conference, 1-10, 2006 | 16 | 2006 |
| DArT: A component-based DRAM area, power, and timing modeling tool HC Shih, PW Luo, JC Yeh, SY Lin, DM Kwai, SL Lu, A Schaefer, CW Wu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 14 | 2014 |
| Transaction level system power estimation method and system WT Hsieh, JC Yeh, HJ Huang, IY Chuang US Patent 8,510,694, 2013 | 14 | 2013 |
| On test and diagnostics of flash memories CT Huang, JC Yeh, YY Shih, RF Huang, CW Wu 13th Asian Test Symposium, 260-265, 2004 | 13 | 2004 |
Jin-Fu LiDepartment of Electrical Engineering, National Central University在 ee.ncu.edu.tw 的电子邮件经过验证
