| A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology S Devarajan, L Singer, D Kelly, T Pan, J Silva, J Brunsilius, D Rey-Losada, ... IEEE Journal of Solid-State Circuits 52 (12), 3204-3218, 2017 | 222 | 2017 |
| Randomly sampling reference ADC for calibration S Devarajan, E Otte, N Rakuljic, CC Speir US Patent 9,525,428, 2016 | 50 | 2016 |
| Efficient calibration of errors in multi-stage analog-to-digital converter CC Speir, E Otte, JP Bray US Patent 9,503,116, 2016 | 27 | 2016 |
| Data handoff between randomized clock domain to fixed clock domain E Otte US Patent 10,057,048, 2018 | 25* | 2018 |
| Microprocessor-assisted calibration for analog-to-digital converter CC Speir, E Otte, N Rakuljic, JP Bray US Patent 9,654,133, 2017 | 14 | 2017 |
| Histogram-based qualification of data used in background or blind calibration of interleaving errors of time-interleaved ADCS E Otte US Patent 10,536,155, 2020 | 7 | 2020 |
| Measuring and correcting non-idealities of a system E Otte US Patent 9,945,901, 2018 | 7 | 2018 |
| In-situ nonlinear calibration of a RF signal chain N Rakuljic, C Speir, E Otte, J Bray, C Petersen, G Manganaro Circuits and Systems (ISCAS), 2018 IEEE International Symposium on, 1-5, 2018 | 5 | 2018 |
| Signal path linearization N Rakuljic, CC Speir, E Otte, C Petersen, JP Bray US Patent 10,340,934, 2019 | 2 | 2019 |
