| Automatic Test Pattern Generation for timing verification and delay testing of RSFQ circuits F Wang, S Gupta 2019 IEEE 37th VLSI Test Symposium (VTS), 1-6, 2019 | 14 | 2019 |
| An effective and efficient automatic test pattern generation (ATPG) paradigm for certifying performance of RSFQ circuits F Wang, SK Gupta IEEE Transactions on Applied Superconductivity 30 (5), 1-11, 2020 | 12 | 2020 |
| Timing Verification for Rapid Single-Flux-Quantum (RSFQ) Logic: New Paradigm and Models F Wang, S Gupta 2019 IEEE International Superconductive Electronics Conference (ISEC), 1-3, 2019 | 11 | 2019 |
| A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits B Zhang, F Wang, S Gupta, M Pedram 2019 IEEE International Superconductive Electronics Conference (ISEC), 1-5, 2019 | 8 | 2019 |
| Methods for testing path delay and static faults in RSFQ circuits M Li, F Wang, S Gupta 2022 IEEE 40th VLSI Test Symposium (VTS), 1-7, 2022 | 7 | 2022 |
| Data-driven fault model development for superconducting logic M Li, F Wang, S Gupta 2020 IEEE International Test Conference (ITC), 1-5, 2020 | 7 | 2020 |
| Static timing analysis (sta) with timing bleed: Certifying much higher performance for rapid single flux quantum (rsfq) logic F Wang, B Zhang, M Pedram, S Gupta Journal of Physics: Conference Series 1559 (1), 012003, 2020 | 5 | 2020 |
| Optimal redundancy designs for cnfet-based circuits D Cheng, F Wang, F Gao, SK Gupta 2014 IEEE 23rd Asian Test Symposium, 25-32, 2014 | 5 | 2014 |
| Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) Logic F Wang, S Gupta 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 4 | 2019 |
| Automated Analog Mixed Signal IP Generatorfor CMOS Technologies M Hassanpourghadi, Q Zhang, P Sharma, J Nam, S Su, S Chowdhury, ... University of Southern California Los Angeles United States, 2019 | 3 | 2019 |
| A heuristic logical effort approach for gate sizing for CNTFET-based circuits FW Da Cheng, F Gao, SK Gupta | 3 | 2014 |
| Verification and Testing of Rapid Single-Flux-Quantum (RSFQ) Circuit for Certifying Logical Correctness and Performance F Wang University of Southern California, 2020 | | 2020 |
| Computer Engineering Technical Report Number CENG-2016-03 F Wang, SK Gupta | | 2016 |
