| FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability D Nagy, G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, ... IEEE Journal of the Electron Devices Society 6, 332-340, 2018 | 213 | 2018 |
| Benchmarking of FinFET, nanosheet, and nanowire FET architectures for future technology nodes D Nagy, G Espineira, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane IEEE Access 8, 53196-53202, 2020 | 91 | 2020 |
| Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs FinFET N Seoane, G Indalecio, E Comesana, M Aldegunde, AJ Garcia-Loureiro, ... IEEE Transactions on Electron Devices 61 (2), 466-472, 2013 | 61 | 2013 |
| Comparison of fin-edge roughness and metal grain work function variability in InGaAs and Si FinFETs N Seoane, G Indalecio, M Aldegunde, D Nagy, MA Elmessary, ... IEEE Transactions on Electron Devices 63 (3), 1209-1216, 2016 | 46 | 2016 |
| Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations MA Elmessary, D Nagy, M Aldegunde, N Seoane, G Indalecio, J Lindberg, ... Solid-State Electronics 128, 17-24, 2017 | 44 | 2017 |
| Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET G Espineira, D Nagy, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane IEEE Electron Device Letters 40 (4), 510-513, 2019 | 37 | 2019 |
| Study of metal-gate work-function variation using Voronoi cells: Comparison of Rayleigh and gamma distributions G Indalecio, AJ Garcia-Loureiro, NS Iglesias, K Kalna IEEE Transactions on Electron Devices 63 (6), 2625-2628, 2016 | 31 | 2016 |
| Metal grain granularity study on a gate-all-around nanowire FET D Nagy, G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, ... IEEE Transactions on Electron Devices 64 (12), 5263-5269, 2017 | 29 | 2017 |
| Impact of cross-sectional shape on 10-nm gate length InGaAs FinFET performance and variability N Seoane, G Indalecio, D Nagy, K Kalna, AJ Garcia-Loureiro IEEE Transactions on Electron Devices 65 (2), 456-462, 2018 | 24 | 2018 |
| Statistical study of the influence of LER and MGG in SOI MOSFET G Indalecio, M Aldegunde, N Seoane, K Kalna, AJ Garcia-Loureiro Semiconductor Science and Technology 29 (4), 045005, 2014 | 23 | 2014 |
| A multi-method simulation toolbox to study performance and variability of nanowire FETs N Seoane, D Nagy, G Indalecio, G Espiñeira, K Kalna, A García-Loureiro Materials 12 (15), 2391, 2019 | 22 | 2019 |
| Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In0.53Ga0.47As GAA MOSFET N Seoane, G Indalecio, E Comesana, AJ Garcia-Loureiro, M Aldegunde, ... IEEE electron device letters 34 (2), 205-207, 2013 | 20 | 2013 |
| 3D simulation study of work-function variability in a 25 nm metal-gate FinFET with curved geometry using Voronoi grains G Indalecio, AJ Garcia-Loureiro, M Aldegunde, K Kalna Proc. 17th Int. Conf. Simul. Semicond. Proc. Devices (SISPAD), 149-152, 2012 | 20 | 2012 |
| Fluctuation sensitivity map: A novel technique to characterise and predict device behaviour under metal grain work-function variability effects G Indalecio, N Seoane, K Kalna, AJ Garcia-Loureiro IEEE Transactions on Electron Devices 64 (4), 1695-1701, 2017 | 17 | 2017 |
| Impact of threshold voltage extraction methods on semiconductor device variability G Espiñera, D Nagy, A García-Loureiro, N Seoane, G Indalecio Solid-State Electronics 159, 165-170, 2019 | 13 | 2019 |
| Drift-diffusion versus Monte Carlo simulated ON-current variability in nanowire FETs D Nagy, G Indalecio, AJ Garcia-Loureiro, G Espineira, MA Elmessary, ... IEEE Access 7, 12790-12797, 2019 | 11 | 2019 |
| Spatial sensitivity of silicon GAA nanowire FETs under line edge roughness variations G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, N Seoane IEEE Journal of the Electron Devices Society 6, 601-610, 2018 | 11 | 2018 |
| Simulation study of scaled In0. 53Ga0. 47As and Si FinFETs for sub-16 nm technology nodes N Seoane, M Aldegunde, D Nagy, MA Elmessary, G Indalecio, ... Semiconductor Science and Technology 31 (7), 075005, 2016 | 10 | 2016 |
| Implementation of numerical methods for nanoscaled semiconductor device simulation using OpenCL E Coronado-Barrientos, A Garcia-Loureiro, G Indalecio, N Seoane 2015 10th Spanish Conference on Electron Devices (CDE), 1-4, 2015 | 8 | 2015 |
| AXC: A new format to perform the SpMV oriented to Intel Xeon Phi architecture in OpenCL E Coronado‐Barrientos, G Indalecio, A García‐Loureiro Concurrency and Computation: Practice and Experience 31 (1), e4864, 2019 | 7 | 2019 |
Antonio Garcia-LoureiroDepartment of Electronics and Computer Science. Universidad de Santiago de Compostela在 usc.es 的电子邮件经过验证
