| Design of DDR4 SDRAM controller MA Islam, MY Arafath, MJ Hasan 8th International Conference on Electrical and Computer Engineering, 148-151, 2014 | 25 | 2014 |
| RVCoreP: An optimized RISC-V soft processor of five-stage pipelining H Miyazaki, T Kanamori, MA Islam, K Kise IEICE Transactions on Information and Systems 103 (12), 2494-2503, 2020 | 17 | 2020 |
| An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA K Matsui, MA Islam, K Kise 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core …, 2019 | 7 | 2019 |
| RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors MA Islam, H Miyazaki, K Kise arXiv preprint arXiv:2010.16171, 2020 | 5 | 2020 |
| Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators MA Islam, K Kise Proceedings of the 13th International Symposium on Highly Efficient …, 2023 | 1 | 2023 |
| An Efficient Resource Shared RISC-V Multicore Architecture MA Islam, K Kise IEICE TRANSACTIONS on Information and Systems 105 (9), 1506-1515, 2022 | 1 | 2022 |
| Efficient resource shared RISC-V multicore processor MA Islam, K Kise 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core …, 2021 | 1 | 2021 |
| A New Synchronous circuit for Elastic Pipeline Architecture MURK Md. Ashraful Islam, Md. Yeasin Arafath International Conference on Materials, Electronics & Information Engineering …, 2015 | | 2015 |
Kise KenjiTokyo Institute of Technology在 cs.titech.ac.jp 的电子邮件经过验证
Kise KenjiTokyo Institute of Technology在 cs.titech.ac.jp 的电子邮件经过验证
Jahid HasanResearcher, Tyndall National Institute, University College Cork在 tyndall.ie 的电子邮件经过验证