| High performance DES encryption in Virtex/sup TM/FPGAs using JBits/sup TM C Patterson Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing …, 2000 | 169 | 2000 |
| Cognitive radio and networking research at Virginia Tech AB MacKenzie, JH Reed, P Athanas, CW Bostian, RM Buehrer, ... Proceedings of the IEEE 97 (4), 660-688, 2009 | 164 | 2009 |
| Consequences and categories of SRAM FPGA configuration SEUs P Graham Proc. Military and Aerospace Programmable Logic Devices, Sept. 2003, 2003 | 155 | 2003 |
| Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices ER Keller, CD Patterson US Patent 6,725,441, 2004 | 130 | 2004 |
| Low-cost and area-efficient FPGA implementations of lattice-based cryptography A Aysu, C Patterson, P Schaumont 2013 IEEE international symposium on hardware-oriented security and trust …, 2013 | 118 | 2013 |
| Parameterizable and reconfigurable debugger core generators CD Patterson, TO Price US Patent 6,802,026, 2004 | 110 | 2004 |
| Systems and methods for automatically mitigating risk of property damage RS Bryant, SM Call, D Hakimi-Boushehri, JH Weekes, J Criswell, T Binion, ... US Patent 10,102,585, 2018 | 103* | 2018 |
| Wires on demand: Run-time communication synthesis for reconfigurable computing P Athanas, J Bowen, T Dunham, C Patterson, J Rice, M Shelburne, ... 2007 International Conference on Field Programmable Logic and Applications …, 2007 | 97* | 2007 |
| Design and evaluation of an active antenna for a 29–47 MHz radio telescope array SW Ellingson, JH Simonetti, CD Patterson IEEE Transactions on Antennas and Propagation 55 (3), 826-831, 2007 | 86 | 2007 |
| Hetergeneous method for determining module placement in FPGAs LJ Hwang, EF Dellinger, S Mitra, S Mohan, CD Patterson, RD Wittig US Patent 6,457,164, 2002 | 79 | 2002 |
| Hardware-facilitated secure software execution environment MT Jones, PM Athanas, CD Patterson, JN Edmison, A Mahar, BJ Muzal, ... US Patent 8,473,754, 2013 | 54 | 2013 |
| Heterogeneous method for determining module placement in FPGAs LJ Hwang, EF Dellinger, S Mitra, S Mohan, CD Patterson, RD Wittig US Patent 6,243,851, 2001 | 54 | 2001 |
| Metawire: using FPGA configuration circuitry to emulate a network-on-chip M Shelburne, C Patterson, P Athanas, M Jones, B Martin, R Fong IET Computers & Digital Techniques 4 (3), 159-169, 2010 | 45 | 2010 |
| JBits™ implementations of the advanced encryption standard (Rijndael) S McMillan, C Patterson International Conference on Field Programmable Logic and Applications, 162-171, 2001 | 44 | 2001 |
| An efficient run-time router for connecting modules in FPGAs J Suris, C Patterson, P Athanas 2008 International Conference on Field Programmable Logic and Applications …, 2008 | 41 | 2008 |
| Semidefinite relaxation-based PAPR-aware precoding for massive MIMO-OFDM systems M Yao, M Carrick, MM Sohul, V Marojevic, CD Patterson, JH Reed IEEE Transactions on Vehicular Technology 68 (3), 2229-2243, 2018 | 38 | 2018 |
| Surveying the hardware trojan threat landscape for the internet-of-things V Venugopalan, CD Patterson Journal of Hardware and Systems Security 2 (2), 131-141, 2018 | 38 | 2018 |
| Method for remapping logic modules to resources of a programmable gate array LJ Hwang, CD Patterson US Patent 6,408,422, 2002 | 37 | 2002 |
| Transient pulses from exploding primordial black holes as a signature of an extra dimension M Kavic, JH Simonetti, SE Cutchin, SW Ellingson, CD Patterson Journal of Cosmology and Astroparticle Physics 2008 (11), 017, 2008 | 35 | 2008 |
| Local adaptive histogram equalization KM Atanassov, JW Nash, SM Verrall, HA Siddiqui US Patent 10,013,764, 2018 | 34* | 2018 |
