Hidden messages in heavy-tails: DCT-domain watermark detection using alpha-stable models A Briassouli, P Tsakalides, A Stouraitis IEEE Transactions on Multimedia 7 (4), 700-715, 2005 | 177 | 2005 |
An RNS Implementation of an Elliptic Curve Point Multiplier DM Schinianakis, AP Fournaris, HE Michail, AP Kakarountas, T Stouraitis IEEE Transactions on Circuits and Systems I: Regular Papers 56 (6), 1202-1213, 2008 | 138 | 2008 |
Efficient RNS Implementation of Elliptic Curve Point Multiplication Over M Esmaeildoust, D Schinianakis, H Javashi, T Stouraitis, K Navi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (8 …, 2012 | 124 | 2012 |
Considering the alternatives in low-power design T Stouraitis, V Paliouras IEEE Circuits and Devices Magazine 17 (4), 22-29, 2001 | 119 | 2001 |
Defect detection and classification on web textile fabric using multiresolution decomposition and neural networks YA Karayiannis, R Stojanovic, P Mitropoulos, C Koulamas, T Stouraitis, ... ICECS'99. Proceedings of ICECS'99. 6th IEEE International Conference on …, 1999 | 96 | 1999 |
Low-power properties of the logarithmic number system V Paliouras, T Stouraitis Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, 229-236, 2001 | 95 | 2001 |
Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST DF Chiper, MNS Swamy, MO Ahmad, T Stouraitis IEEE Transactions on Circuits and Systems I: Regular Papers 52 (6), 1125-1137, 2005 | 93 | 2005 |
A high-speed FPGA implementation of an RSD-based ECC processor H Marzouqi, M Al-Qutayri, K Salah, D Schinianakis, T Stouraitis IEEE Transactions on very large scale integration (vlsi) systems 24 (1), 151-164, 2015 | 89 | 2015 |
Multifunction residue architectures for cryptography D Schinianakis, T Stouraitis IEEE Transactions on Circuits and Systems I: Regular Papers 61 (4), 1156-1169, 2014 | 72 | 2014 |
A new approach to elliptic curve cryptography: an RNS architecture DM Schinianakis, AP Kakarountas, T Stouraitis MELECON 2006-2006 IEEE Mediterranean Electrotechnical Conference, 1241-1245, 2006 | 72 | 2006 |
A systolic array architecture for the discrete sine transform DF Chiper, MNS Swamy, MO Ahmad, T Stouraitis IEEE transactions on signal processing 50 (9), 2347-2354, 2002 | 66 | 2002 |
A radix-4 FFT using complex RNS arithmetic FJ Taylor, G Papadourakis, A Skavantzos, A Stouraitis IEEE Transactions on Computers 100 (6), 573-576, 1985 | 58 | 1985 |
New power-of-2 RNS scaling scheme for cell-based IC design U Meyer-Base, T Stouraitis IEEE transactions on very large scale integration (VLSI) systems 11 (2), 280-283, 2003 | 43 | 2003 |
Multifunction architectures for RNS processors V Paliouras, T Stouraitis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1999 | 41 | 1999 |
A VLSI design methodology for RNS full adder-based inner product architectures DJ Soudris, V Paliouras, T Stouraitis, CE Goutis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1997 | 39 | 1997 |
A low-complexity combinatorial RNS multiplier V Paliouras, K Karagianni, T Stouraitis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001 | 38 | 2001 |
Power analysis of the ARM 7 embedded microprocessor G Sinevriotis, T Stouraitis Proc. 9th Int. Workshop Power and Timing Modeling, Optimization and …, 1999 | 38 | 1999 |
A floating-point processor for fast and accurate sine/cosine evaluation V Paliouras, K Karagianni, T Stouraitis IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000 | 37 | 2000 |
Performance analysis of non-orthogonal multiple access under I/Q imbalance B Selim, S Muhaidat, PC Sofotasios, BS Sharif, T Stouraitis, ... IEEE Access 6, 18453-18468, 2018 | 36 | 2018 |
A hybrid image compression algorithm based on fractal coding and wavelet transform I Andreopoulos, YA Karayianris, T Stouruaitis 2000 IEEE International Symposium on Circuits and Systems (ISCAS) 3, 37-40, 2000 | 36 | 2000 |