| Creating an agile hardware design flow R Bahr, C Barrett, N Bhagdikar, A Carsello, R Daly, C Donovick, D Durst, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 31 | 2020 |
| Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a coarse-grained reconfigurable array for flexible acceleration of dense linear algebra A Carsello, K Feng, T Kong, K Koul, Q Liu, J Melchert, G Nyengele, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI), 70-71, 2022 | 21 | 2022 |
| AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers K Koul, J Melchert, K Sreedhar, L Truong, G Nyengele, K Zhang, Q Liu, ... ACM Transactions on Embedded Computing Systems (TECS), 2022 | 19 | 2022 |
| A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion K Sreedhar, M Horowitz, C Torng Cryptographic Hardware and Embedded Systems (CHES) / IACR Transactions on …, 2022 | 8 | 2022 |
| Compiling halide programs to push-memory accelerators Q Liu, D Huff, J Setter, M Strange, K Feng, K Sreedhar, Z Wang, K Zhang, ... arXiv preprint arXiv:2105.12858, 2021 | 5 | 2021 |
| Enabling and accelerating dynamic vision transformer inference for real-time applications K Sreedhar, J Clemons, R Venkatesan, SW Keckler, M Horowitz arXiv preprint arXiv:2212.02687, 2022 | 4 | 2022 |
| Automating System Configuration. N Tsiskaridze, M Strange, M Mann, K Sreedhar, Q Liu, M Horowitz, ... Formal Methods in Computer-Aided Design (FMCAD), 102-111, 2021 | 4 | 2021 |
| Amber: Coarse-grained reconfigurable array-based soc for dense linear algebra acceleration K Feng, A Carsello, T Kong, K Koul, Q Liu, J Melchert, G Nyengele, ... 2022 IEEE Hot Chips 34 Symposium (HCS), 1-30, 2022 | 2 | 2022 |
| Techniques for balancing dynamic inferencing by machine learning models JL Clemons, K Sreedhar US Patent App. 18/152,528, 2024 | | 2024 |
| Vision Transformer Computation and Resilience for Dynamic Inference K Sreedhar, J Clemons, R Venkatesan, SW Keckler, M Horowitz 2024 IEEE International Symposium on Performance Analysis of Systems and …, 2024 | | 2024 |
| Lake: An Agile Framework for Designing and Automatically Configuring Physical Unified Buffers M Strange, K Sreedhar, M Horowitz Languages, Tools, and Techniques for Accelerator Design (LATTE) Workshop co …, 2024 | | 2024 |
| Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra K Feng, T Kong, K Koul, J Melchert, A Carsello, Q Liu, G Nyengele, ... IEEE Journal of Solid-State Circuits (JSSC), 2023 | | 2023 |
| Augmenting and dynamically configuring a neural network model for real-time systems JL Clemons, K Sreedhar, SW Keckler US Patent App. 17/724,819, 2023 | | 2023 |
| Next Generation Fast Shutter System for LIGO K Sreedhar California Institute of Technology, 2019 | | 2019 |
Mark HorowitzProfessor of Electrical Engineering and Computer Science在 ee.stanford.edu 的电子邮件经过验证
