| Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior K Du Bois, S Eyerman, JB Sartor, L Eeckhout International Symposium on Computer Architecture (ISCA), 2013 | 97 | 2013 |
| Speedup Stacks: Identifying Scaling Bottlenecks in Multi-Threaded Applications S Eyerman, K Du Bois, L Eeckhout IEEE International Symposium on Performance Analysis of Systems and Software …, 2012 | 75 | 2012 |
| Bottle Graphs: Visualizing Scalability Bottlenecks in Multi-Threaded Applications K Du Bois, JB Sartor, S Eyerman, L Eeckhout ACM SIGPLAN 2013 Conference on Object Oriented Programming, Systems …, 2013 | 63 | 2013 |
| Per-thread cycle accounting in multicore processors K Du Bois, S Eyerman, L Eeckhout ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-22, 2013 | 43 | 2013 |
| Near-Side Prefetch Throttling: Adaptive Prefetching for High-Performance Many-Core Processors W Heirman, K Du Bois, Y Vandriessche, S Eyerman, I Hur International Conference on Parallel Architectures and Compilation …, 2018 | 38 | 2018 |
| Many-Core Graph Workload Analysis S Eyerman, W Heirman, K Du Bois, JB Fryman, I Hur International Conference for High Performance Computing, Networking, Storage …, 2018 | 30 | 2018 |
| Independent tuning of multiple hardware prefetchers W Heirman, K Du Bois, Y VANDRIESSCHE, S EYERMAN, I Hur US Patent App. 15/718,845, 2019 | 28* | 2019 |
| PIUMA: Programmable Integrated Unified Memory Architecture S Aananthakrishnan, NK Ahmed, V Cave, M Cintra, Y Demir, K Du Bois, ... arXiv preprint arXiv:2010.06277, 2020 | 25 | 2020 |
| SWEEP: Evaluating computer system energy efficiency using synthetic workloads K Du Bois, T Schaeps, S Polfliet, F Ryckbosch, L Eeckhout International Conference on High Performance and Embedded Architectures and …, 2011 | 20 | 2011 |
| Multi-stage CPI stacks S Eyerman, W Heirman, K Du Bois, I Hur IEEE Computer Architecture Letters 17 (1), 55-58, 2017 | 8 | 2017 |
| Projecting performance for PIUMA using down-scaled simulation S Eyerman, W Heirman, Y Demir, K Du Bois, I Hur 2020 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2020 | 7 | 2020 |
| Technologies for processor simulation modeling with machine learning Y Vandriessche, W Heirman, I Hur, K Du Bois, S Eyerman US Patent App. 15/638,727, 2019 | 7 | 2019 |
| The Intel programmable and integrated unified memory architecture graph analytics processor S Aananthakrishnan, S Abedin, V Cavé, F Checconi, K Du Bois, ... IEEE Micro 43 (5), 78-87, 2023 | 5 | 2023 |
| Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics W Heirman, I Hur, U Echeruo, S Eyerman, K Du Bois US Patent 10,621,099, 2020 | 5 | 2020 |
| Automatic Sublining for Efficient Sparse Memory Accesses W Heirman, S Eyerman, K Du Bois, I Hur ACM Transactions on Architecture and Code Optimization (TACO) 18 (3), 1-23, 2021 | 4 | 2021 |
| Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks S Eyerman, W Heirman, K Du Bois, I Hur IEEE International Symposium on Performance Analysis of Systems and Software …, 2018 | 4 | 2018 |
| Analyzing the Scalability of Managed Language Applications with Speedup Stacks JB Sartor, K Du Bois, S Eyerman, L Eeckhout IEEE International Symposium on Performance Analysis of Systems and Software …, 2017 | 4 | 2017 |
| Indirect memory fetcher S EYERMAN, W Heirman, K Du Bois, I Hur, JB Fryman US Patent App. 15/996,184, 2019 | 2 | 2019 |
| Accurate and Scalable Many-Node Simulation S Eyerman, W Heirman, K Du Bois, I Hur arXiv preprint arXiv:2401.09877, 2024 | 1 | 2024 |
| System, apparatus and method for dynamic automatic sub-cacheline granularity memory access control W Heirman, S Eyerman, K Du Bois, I Hur, JB Fryman US Patent 10,942,851, 2021 | 1 | 2021 |
Stijn EyermanResearch Scientist, Intel Belgium在 intel.com 的电子邮件经过验证
