| SpecC: Specification Language and Methodology DD Gajski, J Zhu, R Dömer, A Gerstlauer, S Zhao Springer Science & Business Media, 2000 | 920* | 2000 |
| DeepThings: Distributed adaptive deep learning inference on resource-constrained IoT edge clusters Z Zhao, KM Barijough, A Gerstlauer IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 438 | 2018 |
| Embedded System Design: Modeling, Synthesis and Verification DD Gajski, S Abdi, A Gerstlauer, G Schirner Springer Science & Business Media, 2009 | 419 | 2009 |
| Electronic system-level synthesis methodologies A Gerstlauer, C Haubelt, AD Pimentel, TP Stefanov, DD Gajski, J Teich IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 247 | 2009 |
| RTOS modeling for system level design A Gerstlauer, H Yu, DD Gajski Embedded Software for SoC, 55-68, 2003 | 238 | 2003 |
| System Design: A Practical Guide with SpecC A Gerstlauer, R Dömer, J Peng, DD Gajski Springer Science & Business Media, 2001 | 201* | 2001 |
| Modeling and synthesis of quality-energy optimal approximate adders J Miao, K He, A Gerstlauer, M Orshansky Proceedings of the international conference on computer-aided design, 728-735, 2012 | 169 | 2012 |
| System-on-chip environment: A SpecC-based framework for heterogeneous MPSoC design R Dömer, A Gerstlauer, J Peng, D Shin, L Cai, H Yu, S Abdi, DD Gajski EURASIP Journal on Embedded Systems 2008, 1-13, 2008 | 162 | 2008 |
| Reliability-aware design to suppress aging H Amrouch, B Khaleghi, A Gerstlauer, J Henkel Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 114 | 2016 |
| Approximate logic synthesis under general error magnitude and frequency constraints J Miao, A Gerstlauer, M Orshansky 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 779-786, 2013 | 96 | 2013 |
| High-level synthesis of approximate hardware under joint precision and voltage scaling S Lee, LK John, A Gerstlauer Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 87 | 2017 |
| Codesign tradeoffs for high-performance, low-power linear algebra architectures A Pedram, RA Van De Geijn, A Gerstlauer IEEE Transactions on Computers 61 (12), 1724-1736, 2012 | 78 | 2012 |
| Accurate phase-level cross-platform power and performance estimation X Zheng, LK John, A Gerstlauer Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 74 | 2016 |
| Retargetable profiling for rapid, early system-level design space exploration L Cai, A Gerstlauer, D Gajski Proceedings of the 41st annual Design Automation Conference, 281-286, 2004 | 74 | 2004 |
| Exploiting errors for efficiency: A survey from circuits to applications P Stanley-Marbell, A Alaghi, M Carbin, E Darulova, L Dolecek, ... ACM Computing Surveys (CSUR) 53 (3), 1-39, 2020 | 71 | 2020 |
| System-level abstraction semantics A Gerstlauer, DD Gajski Proceedings of the 15th international symposium on System Synthesis, 231-236, 2002 | 71 | 2002 |
| Horizontal side-channel vulnerabilities of post-quantum key exchange protocols A Aysu, Y Tobah, M Tiwari, A Gerstlauer, M Orshansky 2018 IEEE international symposium on hardware oriented security and trust …, 2018 | 69 | 2018 |
| The next generation of virtual prototyping: Ultra-fast yet accurate simulation of HW/SW systems O Bringmann, W Ecker, A Gerstlauer, A Goyal, D Mueller-Gritschneder, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 67 | 2015 |
| Multi-level approximate logic synthesis under general error constraints J Miao, A Gerstlauer, M Orshansky 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 504-510, 2014 | 62 | 2014 |
| RTOS scheduling in transaction level models H Yu, A Gerstlauer, D Gajski Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware …, 2003 | 61 | 2003 |
Daniel D. GajskiProfessor of Computer science, University of California at Irvine在 uci.edu 的电子邮件经过验证
