| 16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced … J Kim, H Yoon, Y Lim, Y Lee, Y Cho, T Seong, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 258-260, 2019 | 68 | 2019 |
| A low-integrated-phase-noise 27–30-GHz injection-locked frequency multiplier with an ultra-low-power frequency-tracking loop for mm-wave-band 5G transceivers S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi IEEE Journal of Solid-State Circuits 53 (2), 375-388, 2017 | 63 | 2017 |
| A− 31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection … H Yoon, J Kim, S Park, Y Lim, Y Lee, J Bang, K Lim, J Choi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 366-368, 2018 | 54 | 2018 |
| A Wideband Dual-Mode -VCO With a Switchable Gate-Biased Active Core H Yoon, Y Lee, JJ Kim, J Choi IEEE Transactions on Circuits and Systems II: Express Briefs 61 (5), 289-293, 2014 | 46 | 2014 |
| A low-jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique Y Lee, T Seong, S Yoo, J Choi IEEE Journal of Solid-State Circuits 53 (4), 1192-1202, 2017 | 45 | 2017 |
| A 0.56–2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G–4G Multistandard Cellular Transceivers H Yoon, Y Lee, Y Lim, GY Tak, HT Kim, YC Ho, J Choi IEEE Journal of Solid-State Circuits 51 (3), 614-625, 2016 | 40 | 2016 |
| A 320-fs RMS jitter and–75-dBc reference-spur ring-DCO-based digital PLL using an optimal-threshold TDC T Seong, Y Lee, S Yoo, J Choi IEEE Journal of Solid-State Circuits 54 (9), 2501-2512, 2019 | 39 | 2019 |
| An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators J Kim, Y Lim, H Yoon, Y Lee, H Park, Y Cho, T Seong, J Choi IEEE Journal of Solid-State Circuits 54 (12), 3466-3477, 2019 | 37 | 2019 |
| 19.2 A PVT-robust− 39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase … S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi 2017 IEEE International Solid-State Circuits Conference (ISSCC), 324-325, 2017 | 36 | 2017 |
| 17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator … T Seong, Y Lee, C Hwang, J Lee, H Park, KJ Lee, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2020 | 34 | 2020 |
| An external capacitor-less ultralow-dropout regulator using a loop-gain stabilizing technique for high power-supply rejection over a wide range of load current Y Lim, J Lee, Y Lee, SS Song, HT Kim, O Lee, J Choi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (11 …, 2017 | 33 | 2017 |
| A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator forPLLs Y Lee, M Kim, T Seong, J Choi IEEE Transactions on Circuits and Systems I: Regular Papers 62 (3), 635-644, 2014 | 27 | 2014 |
| 32.1 A 365fsrms-jitter and-63dBc-Fractional spur 5.3 GHz-ring-DCO-based fractional-N DPLL using a DTC second/third-order nonlinearity cancelation and a probability-density … H Park, C Hwang, T Seong, Y Lee, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 442-444, 2021 | 26 | 2021 |
| A PVT-robust −59-dBc reference spur and 450-fsRMSjitter injection-locked clock multiplier using a voltage-domain period-calibrating loop Y Lee, H Yoon, M Kim, J Choi 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 25 | 2016 |
| A− 242dB FOM and− 75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC T Seong, Y Lee, S Yoo, J Choi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2018 | 22 | 2018 |
| 30.9 A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope … S Yoo, S Choi, Y Lee, T Seong, Y Lim, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 490-492, 2019 | 20 | 2019 |
| A− 242-dB FOM and− 71-dBc reference spur ring-VCO-based ultra-low-jitter switched-loop-filter PLL using a fast phase-error correction technique T Seong, Y Lee, S Yoo, J Choi 2017 Symposium on VLSI Circuits, C186-C187, 2017 | 20 | 2017 |
| A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability … C Hwang, H Park, Y Lee, T Seong, J Choi IEEE Journal of Solid-State Circuits 57 (9), 2841-2855, 2022 | 19 | 2022 |
| A low-jitter and low-reference-spur ring-VCO-based injection-locked clock multiplier using a triple-point background calibrator S Yoo, S Choi, Y Lee, T Seong, Y Lim, J Choi IEEE Journal of Solid-State Circuits 56 (1), 298-309, 2020 | 19 | 2020 |
| 17.1 A −240dB-FoMjitter and −115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged … Y Lee, T Seong, J Lee, C Hwang, H Park, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 266-268, 2020 | 18 | 2020 |
Jaehyouk ChoiAssociate Professor of Seoul National University在 snu.ac.kr 的电子邮件经过验证
