| A slew-rate controlled output driver using PLL as compensation circuit SK Shin, SM Jung, JH Seo, ML Ko, JW Kim IEEE Journal of Solid-State Circuits 38 (7), 1227-1233, 2003 | 47 | 2003 |
| A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillator SM Jung, JM Roveda Sixteenth International Symposium on Quality Electronic Design, 103-106, 2015 | 22 | 2015 |
| Phase locked loop integrated circuits having fast locking characteristics and methods of operating same SM Jung, JH Kim US Patent 7,292,078, 2007 | 13 | 2007 |
| Design of a feedback digitally controlled oscillator for linearity enhancement SM Jung, JM Roveda 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | 7 | 2015 |
| Design of low jitter phase-locked loop with closed loop voltage controlled oscillator SM Jung, JM Roveda 2015 IEEE 16th Annual Wireless and Microwave Technology Conference (WAMICON …, 2015 | 7 | 2015 |
| Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock SM Jung US Patent 7,388,412, 2008 | 5 | 2008 |
| A Low Jitter Digital Phase-Locked Loop With a Hybrid Analog/Digital PI Control SM Jung, JM Roveda New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International, 2015 | 4 | 2015 |
| A 320MHz–2.56 GHz low jitter phase-locked loop with adaptive-bandwidth technique SM Jung, JM Roveda 2015 28th IEEE International System-on-Chip Conference (SOCC), 40-43, 2015 | 3 | 2015 |
| Design of the voltage clamp delay cell VCO using quadrature phase for low phase noise and high speed operation IW Seo, WB Choi, SM Jung, MY Sung International Conference on VLSI and CAD, 570 - 573, 1999 | 2 | 1999 |
| Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System SM Jung The University of Arizona., 2016 | 1 | 2016 |
| Design of a low jitter digital PLL with low input frequency S Jung | | 2012 |
