| Body-bias-driven design strategy for area-and performance-efficient CMOS circuits M Meijer, JP De Gyvez IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (1), 42-51, 2010 | 49 | 2010 |
| Testing and diagnosis of power switches in SOCs SK Goel, M Meijer, JP de Gyvez Eleventh IEEE European Test Symposium (ETS'06), 6 pp.-150, 2006 | 44 | 2006 |
| On-chip digital power supply control for system-on-chip applications M Meijer, J Pineda de Gyvez, R Otten Proceedings of the 2005 international symposium on Low power electronics and …, 2005 | 39 | 2005 |
| Characterization of STI edge effects on CMOS variability N Wils, HP Tuinhout, M Meijer IEEE Transactions on Semiconductor Manufacturing 22 (1), 59-65, 2009 | 36 | 2009 |
| A forward body bias generator for digital CMOS circuits with supply voltage scaling M Meijer, JP de Gyvez, B Kup, B van Uden, P Bastiaansen, M Lammers, ... Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 34 | 2010 |
| Adaptive techniques for dynamic processor optimization: theory and practice A Wang, S Naffziger Springer Science & Business Media, 2008 | 32 | 2008 |
| Technology exploration for adaptive power and frequency scaling in 90nm CMOS M Meijer, F Pessolano, JP de Gyvez Proceedings of the 2004 international symposium on Low power electronics and …, 2004 | 32 | 2004 |
| Technology scaling of critical charges in storage circuits based on cross-coupled inverter-pairs T Heijmen, B Kruseman, R van Veen, M Meijer 2004 IEEE International Reliability Physics Symposium. Proceedings, 675-676, 2004 | 26 | 2004 |
| Digital systems power management for high performance mixed signal platforms A Kapoor, C Groot, GV Piqué, H Fatemi, J Echeverri, L Sevat, M Vertregt, ... IEEE Transactions on Circuits and Systems I: Regular Papers 61 (4), 961-975, 2014 | 24 | 2014 |
| A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias GV Piqué, M Meijer 2011 Proceedings of the ESSCIRC (ESSCIRC), 379-382, 2011 | 21 | 2011 |
| Post-silicon tuning capabilities of 45nm low-power CMOS digital circuits M Meijer, B Liu, R Van Veen, JP De Gyvez 2009 Symposium on VLSI Circuits, 110-111, 2009 | 21 | 2009 |
| Ultra-low-power digital design with body biasing for low area and performance-efficient operation M Meijer, JP De Gyvez, A Kapoor Journal of Low Power Electronics 6 (4), 521-532, 2010 | 18 | 2010 |
| Technological boundaries of voltage and frequency scaling for power performance tuning M Meijer, JP de Gyvez Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice …, 2008 | 17 | 2008 |
| Influence of STI stress on drain current matching in advanced CMOS N Wils, H Tuinhout, M Meijer 2008 IEEE International Conference on Microelectronic Test Structures, 238-243, 2008 | 14 | 2008 |
| Efficient testing and diagnosis of faulty power switches in SOCs SK Goel, M Meijer, JP De Gyvez IET Computers & Digital Techniques 1 (3), 230-236, 2007 | 13 | 2007 |
| Testable integrated circuit and IC test method JR Vazquez, LE Villagra, RIMP Meijer US Patent 8,138,783, 2012 | 11 | 2012 |
| Testable integrated circuit and ic test method S Goel, JJP De Gyvez, RLMP Meijer US Patent App. 12/160,409, 2010 | 11 | 2010 |
| Body bias driven design synthesis for optimum performance per area M Meijer, JP de Gyvez 2010 11th International Symposium on Quality Electronic Design (ISQED), 472-477, 2010 | 11 | 2010 |
| Energy-efficient FPGA interconnect design M Meijer, R Krishnan, M Bennebroek Proceedings of the Design Automation & Test in Europe Conference 2, 1-6, 2006 | 11 | 2006 |
| Clock buffer V Sharma, RIMP Meijer, JP de Gyvez US Patent 9,065,439, 2015 | 10 | 2015 |
Jose Pineda de GyvezNXP Semiconductors and Eindhoven University of Technology在 tue.nl 的电子邮件经过验证
