Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS R Vaddi, S Dasgupta, RP Agarwal IEEE Transactions on Electron Devices 57 (3), 654-664, 2010 | 192* | 2010 |
Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS S DasGupta, AF Witulski, BL Bhuva, ML Alles, RA Reed, OA Amusan, ... IEEE Transactions on Nuclear Science 54 (6), 2407-2412, 2007 | 131 | 2007 |
Nanoscale FinFET based SRAM cell design: Analysis of performance metric, process variation, underlapped FinFET, and temperature effect B Raj, AK Saxena, S Dasgupta IEEE Circuits and Systems Magazine 11 (3), 38-50, 2011 | 130 | 2011 |
Antifungal Activity of Some Plant Extracts Against Fungal Pathogens of Tea (Camellia sinensis.) D Saha, S Dasgupta, A Saha Pharmaceutical biology 43 (1), 87-91, 2005 | 100 | 2005 |
A Comparative Study of 6T, 8T and 9T Decanano SRAM cell P Athe, S Dasgupta 2009 IEEE Symposium on Industrial Electronics & Applications 2, 889-894, 2009 | 97 | 2009 |
Surface potential and drain current analytical model of gate all around triple metal TFET N Bagga, S Dasgupta IEEE Transactions on Electron Devices 64 (2), 606-613, 2017 | 83 | 2017 |
High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 60 (10), 3371-3377, 2013 | 77 | 2013 |
Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 61 (11), 3579-3585, 2014 | 76 | 2014 |
Demonstration of a novel two source region tunnel FET N Bagga, A Kumar, S Dasgupta IEEE Transactions on Electron Devices 64 (12), 5256-5262, 2017 | 75 | 2017 |
Design and analysis of analog performance of dual-k spacer underlap N/P-FinFET at 12 nm gate length A Nandi, AK Saxena, S Dasgupta IEEE transactions on electron devices 60 (5), 1529-1535, 2013 | 74 | 2013 |
Recent trend of FinFET devices and its challenges: A review RS Pal, S Sharma, S Dasgupta 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), 150-154, 2017 | 70 | 2017 |
Analytical modeling of a double gate MOSFET considering source/drain lateral Gaussian doping profile A Nandi, AK Saxena, S Dasgupta IEEE Transactions on Electron Devices 60 (11), 3705-3709, 2013 | 65 | 2013 |
Asymmetric dual-spacer trigate FinFET device-circuit codesign and its variability analysis PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 62 (4), 1105-1112, 2015 | 59 | 2015 |
FPGA: An efficient and promising platform for real-time image processing applications S Mittal, S Gupta, S Dasgupta National Conference On Research and Development In Hardware Systems (CSI-RDHS), 2008 | 57 | 2008 |
Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device B Raj, AK Saxena, S Dasgupta Microelectronics International 26 (1), 53-63, 2009 | 56 | 2009 |
Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field M Yadav, A Bulusu, S Dasgupta Microelectronics Journal 44 (12), 1251-1259, 2013 | 54 | 2013 |
System generator: The state-of-art FPGA design tool for dsp applications S Mittal, S Gupta, S Dasgupta Third International Innovative Conference On Embedded Systems, Mobile …, 2008 | 44 | 2008 |
Impact of dual-k spacer on analog performance of underlap FinFET A Nandi, AK Saxena, S Dasgupta Microelectronics Journal 43 (11), 883-887, 2012 | 38 | 2012 |
Spacer engineering-based high-performance reconfigurable FET with low off current characteristics A Bhattacharjee, M Saikiran, A Dutta, B Anand, S Dasgupta IEEE Electron Device Letters 36 (5), 520-522, 2015 | 37 | 2015 |
Radiation effects in Si-NW GAA FET and CMOS inverter: A TCAD simulation study G Kaushal, SS Rathod, S Maheshwaram, SK Manhas, AK Saxena, ... IEEE Transactions on Electron Devices 59 (5), 1563-1566, 2012 | 37 | 2012 |