| Selection circuit for accurate memory read operations BQ Le, M Achter, L Cleveland, P Chen US Patent 6,768,679, 2004 | 392 | 2004 |
| Scheme for page erase and erase verify in a non-volatile memory array PL Chen, MSC Chung, SC Hollmer, V Leung, BQ Le, M Yano US Patent 5,995,417, 1999 | 248 | 1999 |
| Erase verify scheme for NAND flash SC Hollmer, CY Hu, BQ Le, PL Chen, J Su, R Gutala, C Bill US Patent 6,009,014, 1999 | 162 | 1999 |
| Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells SK Yachareni, K Kurihara, BQ Le, MSC Chung US Patent 6,370,061, 2002 | 146 | 2002 |
| Precharging mechanism and method for NAND-based flash memory devices A Yang, S Hollmer, BQ Le US Patent 6,175,523, 2001 | 138 | 2001 |
| Soft program and soft program verify of the core cells in flash memory array SK Yachareni, DG Hamilton, BQ Le, K Kurihara US Patent 6,493,266, 2002 | 113 | 2002 |
| High-voltage CMOS level shifter BQ Le, S Kawamura, PL Chen, S Hollmer US Patent 5,821,800, 1998 | 108 | 1998 |
| A 5.6 MB/s 64Gb 4b/cell NAND flash memory in 43nm CMOS C Trinh, N Shibata, T Nakano, M Ogawa, J Sato, Y Takeyama, K Isobe, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 103 | 2009 |
| Drain side sensing scheme for virtual ground flash eprom array with adjacent bit charge and hold BQ Le, PL Chen, MA Van Buskirk, SK Yachareni, MSC Chung, K Kurihara, ... US Patent 6,510,082, 2003 | 85 | 2003 |
| A 34 MB/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology RA Cernea, L Pham, F Moogat, S Chan, B Le, Y Li, S Tsao, TY Tseng, ... IEEE Journal of Solid-State Circuits 44 (1), 186-194, 2008 | 82 | 2008 |
| Method for improving read margin in a flash memory device BQ Le, PL Chen US Patent 6,643,177, 2003 | 70 | 2003 |
| Resistive RAM endurance: Array-level characterization and correction techniques targeting deep learning applications A Grossi, E Vianello, MM Sabry, M Barlas, L Grenouillet, J Coignus, ... IEEE Transactions on Electron Devices 66 (3), 1281-1288, 2019 | 66 | 2019 |
| Modulated charge pump with uses an analog to digital converter to compensate for supply voltage variations BQ Le, PL Chen US Patent 6,424,570, 2002 | 64 | 2002 |
| Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell BQ Le, A Grossi, E Vianello, T Wu, G Lama, E Beigne, HSP Wong, S Mitra IEEE Transactions on Electron Devices 66 (1), 641-646, 2019 | 62* | 2019 |
| A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology K Kanda, M Koyanagi, T Yamamura, K Hosono, M Yoshihara, T Miwa, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 62 | 2008 |
| A 34MB/s-program-throughput 16Gb MLC NAND with all-bitline architecture in 56nm R Cernea, L Pham, F Moogat, S Chan, B Le, Y Li, S Tsao, TY Tseng, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 61 | 2008 |
| Algorithm dynamic reference programming BQ Le, PL Chen US Patent 6,690,602, 2004 | 61 | 2004 |
| 128Gb 3b/Cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode Y Li, S Lee, K Oowada, H Nguyen, Q Nguyen, N Mokhlesi, C Hsu, J Li, ... 2012 IEEE International Solid-State Circuits Conference, 436-437, 2012 | 57 | 2012 |
| Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage BQ Le, M Yano, SK Yachareni US Patent 6,535,424, 2003 | 45 | 2003 |
| Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device SC Hollmer, PL Chen, BQ Le US Patent 5,638,326, 1997 | 45 | 1997 |
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