| BLADE: An in-cache computing architecture for edge devices WA Simon, YM Qureshi, M Rios, A Levisse, M Zapater, D Atienza IEEE Transactions on Computers 69 (9), 1349-1363, 2020 | 73 | 2020 |
| A fast, reliable and wide-voltage-range in-memory computing architecture W Simon, J Galicia, A Levisse, M Zapater, D Atienza Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 39 | 2019 |
| SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures A Levisse, B Giraud, JP Noel, M Moreau, JM Portal 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2015 | 32 | 2015 |
| Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications G Sassine, C Nail, L Tillie, DA Robayo, A Levisse, C Cagli, KE Hajjam, ... 2018 IEEE International Reliability Physics Symposium (IRPS), P-MY. 2-1-P-MY …, 2018 | 31 | 2018 |
| Graphene-based wireless agile interconnects for massive heterogeneous multi-chip processors S Abadal, R Guirado, H Taghvaee, A Jain, EP de Santana, PH Bolívar, ... IEEE wireless communications 30 (4), 162-169, 2022 | 28 | 2022 |
| BLADE: A bitline accelerator for devices on the edge WA Simon, YM Qureshi, A Levisse, M Zapater, D Atienza Proceedings of the 2019 on Great Lakes Symposium on VLSI, 207-212, 2019 | 28 | 2019 |
| Design and simulation of a 128 kb embedded nonvolatile memory based on a hybrid RRAM (HfO2)/28 nm FDSOI CMOS technology JM Portal, M Bocquet, S Onkaraiah, M Moreau, H Aziza, D Deleruyelle, ... IEEE Transactions on Nanotechnology 16 (4), 677-686, 2017 | 28 | 2017 |
| In-depth investigation of programming and reading operations in RRAM cells integrated with Ovonic Threshold Switching (OTS) selectors M Alayan, E Vianello, G Navarro, C Carabasse, S La Barbera, A Verdy, ... 2017 IEEE International Electron Devices Meeting (IEDM), 2.3. 1-2.3. 4, 2017 | 24 | 2017 |
| Architecture, design and technology guidelines for crosspoint memories A Levisse, B Giraud, JP Noel, M Moreau, JM Portal 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2017 | 20 | 2017 |
| Write termination circuits for RRAM: A holistic approach from technology to application considerations A Levisse, M Bocquet, M Rios, M Alayan, M Moreau, E Nowak, G Molas, ... Ieee Access 8, 109297-109308, 2020 | 15 | 2020 |
| Alpine: Analog in-memory acceleration with tight processor integration for deep learning J Klein, I Boybat, YM Qureshi, M Dazzi, A Levisse, G Ansaloni, M Zapater, ... IEEE Transactions on Computers 72 (7), 1985-1998, 2022 | 14 | 2022 |
| An associativity-agnostic in-cache computing architecture optimized for multiplication M Rios, W Simon, A Levisse, M Zapater, D Atienza 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 13 | 2019 |
| Switching event detection and self-termination programming circuit for energy efficient reram memory arrays M Alayan, E Muhr, A Levisse, M Bocquet, M Moreau, E Nowak, G Molas, ... IEEE Transactions on Circuits and Systems II: Express Briefs 66 (5), 748-752, 2019 | 13 | 2019 |
| Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence C Maneux, C Mukherjee, M Deng, M Dubourg, L Réveil, G Bordea, ... 2021 IEEE International Electron Devices Meeting (IEDM), 15.6. 1-15.6. 4, 2021 | 12 | 2021 |
| A flexible in-memory computing architecture for heterogeneously quantized CNNs F Ponzina, M Rios, G Ansaloni, A Levisse, D Atienza 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 164-169, 2021 | 12 | 2021 |
| RRAM crossbar arrays for storage class memory applications: Throughput and density considerations A Levisse, B Giraud, JP Noel, M Moreau, JM Portal 2018 Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2018 | 10 | 2018 |
| New perspectives for multicore architectures using advanced technologies F Clermidy, P Vivet, D Dutoit, Y Thonnart, JL Gonzales, JP Noël, B Giraud, ... 2016 IEEE International Electron Devices Meeting (IEDM), 35.1. 1-35.1. 4, 2016 | 10 | 2016 |
| Bit-line computing for CNN accelerators co-design in edge AI inference M Rios, F Ponzina, A Levisse, G Ansaloni, D Atienza IEEE Transactions on Emerging Topics in Computing 11 (2), 358-372, 2023 | 9 | 2023 |
| Rram-vac: A variability-aware controller for rram-based memory architectures S Tuli, M Rios, A Levisse, DA ESL 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 181-186, 2020 | 9 | 2020 |
| Functionality enhanced memories for edge-AI embedded systems A Levisse, M Rios, WA Simon, PE Gaillardon, D Atienza 2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2019 | 9 | 2019 |
Portal Jean-MichelFull Professor Aix-Marseille Université - IM2NP在 univ-amu.fr 的电子邮件经过验证
