| A novel extended source TFET with δp+-SiGe layer J Talukdar, G Rawat, K Mummaneni Silicon 12 (10), 2273-2281, 2020 | 55 | 2020 |
| A non-uniform silicon TFET design with dual-material source and compressed drain J Talukdar, K Mummaneni Applied Physics A 126 (1), 81, 2020 | 32 | 2020 |
| Comparative Analysis of the Effects of Trap Charges on Single-and Double-Gate Extended-Source Tunnel FET with dp SiGe Pocket Layer J Talukdar, G Rawat, K Singh, K Mummaneni | 25 | 2020 |
| A survey on FDTD-based interconnect modeling NS Murthy, M Kavicharan Journal of Circuits, Systems and Computers 24 (01), 1530001, 2015 | 9 | 2015 |
| An efficient delay estimation model for high speed VLSI interconnects M Kavicharan, NS Murthy, NB Rao 2013 International Conference on Advances in Computing, Communications and …, 2013 | 7 | 2013 |
| Modeling and analysis of on-chip single and H-tree distributed RLC interconnects M Kavicharan, NS Murthy, NB Rao, A Prathima Circuits, Systems, and Signal Processing 35, 3049-3065, 2016 | 4 | 2016 |
| Efficient delay and crosstalk estimation models for current-mode high speed interconnects under ramp input M Kavicharan, NS Murthy, N Bheema Rao Journal of Circuits, Systems and Computers 23 (06), 1450082, 2014 | 4 | 2014 |
| A closed-form delay estimation model for current-mode high speed VLSI interconnects M Kavicharan, NS Murthy, NB Rao 2013 The International Conference on Technological Advances in Electrical …, 2013 | 4 | 2013 |
| A closed-form delay estimation model for current-mode high speed VLSI interconnects M Kavicharan, NS Murthy, NB Rao WSEAS Transactions on Communications 20, 198-202, 2021 | 2 | 2021 |
| Noise behavior of SG-ESTFET with various interface trap charges KM J. Talukdar International Conference on Computational Performance Evaluation (ComPE …, 2020 | 1 | 2020 |
| A Novel Delay and Overshoot Estimation model for VLSI Global Interconnects M Kavicharan, NS Murthy, NB Rao 18th international Conference on Circuits, Systems, Communications and …, 2014 | 1 | 2014 |
| An Efficient Distributed Tree Structure Modelling for VLSI circuits M Kavicharan, NS Murthy, NB Rao Proceedings of the 2014 International Conference on Circuits, Systems …, 2014 | 1 | 2014 |
| Transient Analysis of VLSI Tree Interconnects based on Matrix Pade Type Approximation M Kavicharan, NS Murthy, NB Rao WSEAS Transactions on Circuits and Systems 13, 360-367, 2014 | | 2014 |
| Modal Decomposition-based VLSI Interconnect Delay Modeling Proceedings of International Conference on Solid-State and Integrated …, 2012 | | 2012 |
| An Efficient Hybrid Voltage/Current mode Signaling Scheme for On-Chip Interconnects M Kavicharan, NS Murthy, NB Rao | | |
