| Impact of Gate–Source Overlap on the Device/Circuit Analog Performance of Line TFETs A Acharya, AB Solanki, S Glass, QT Zhao, B Anand IEEE Transactions on Electron Devices 66 (9), 4081-4086, 2019 | 34 | 2019 |
| Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective A Acharya, AB Solanki, S Dasgupta, B Anand IEEE Transactions on Electron Devices 65 (1), 322-330, 2017 | 32 | 2017 |
| FPGA Based Non Uniform Illumination Correction in Image Processing Application 2 A Acharya, R Mehra, VS Takher EBSCO, university of Karlsruhe, Germany, 2009 | 22 | 2009 |
| Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight S Srivastava, S Panwar, A Acharya IEEE Transactions on Electron Devices 69 (8), 4693-4699, 2022 | 20 | 2022 |
| A Novel Extraction Method for Tunnel FETs and Its Implication on Analog Design A Acharya, S Dasgupta, B Anand IEEE Transactions on Electron Devices 64 (2), 629-633, 2016 | 16 | 2016 |
| Emerging Low-Power Semiconductor Devices: Applications for Future Technology Nodes S Tayal, AK Upadhyay, D Kumar, SB Rahi CRC Press, 2022 | 14 | 2022 |
| Detection of Defects in Glass Sheet using CS C based Segmentation Method T Singh, RL Dua, S Agrawal, A Acharya International Journal of Computer Applications 68 (14), 2013 | 13 | 2013 |
| Investigation of Self-Heating Effect in Tree-FETs by Interbridging Stacked Nanosheets: A Reliability Perspective S Srivastava, M Shashidhara, A Acharya IEEE Transactions on Device and Materials Reliability 23 (1), 58-63, 2022 | 12 | 2022 |
| Exploration of 9T SRAM Cell for In Memory Computing Application AK Gupta, A Acharya 2021 Devices for Integrated Circuit (DevIC), 461-465, 2021 | 8 | 2021 |
| Performance evaluation of high-κ dielectric ferro-spacer engineered Si/SiGe hetero-junction line TFETs: a TCAD approach S Panwar, S Srivastava, M Shashidhara, A Acharya IEEE Transactions on Dielectrics and Electrical Insulation 30 (3), 1066-1071, 2023 | 6 | 2023 |
| Investigation of Field-Free Switching of 2-D Material-Based Spin–Orbit Torque Magnetic Tunnel Junction M Shashidhara, V Nehra, S Srivatsava, S Panwar, A Acharya IEEE Transactions on Electron Devices 70 (3), 1430-1435, 2023 | 5 | 2023 |
| Performance Investigation of Source/Drain Extension Region on Nanosheet FET: A Digital Design Perspective S Srivastava, S Panwar, M Shashidhara, N Bagga, D Joshi, A Acharya 2023 Silicon Nanoelectronics Workshop (SNW), 79-80, 2023 | 3 | 2023 |
| Interface trap charges analysis on DC and high frequency characteristics of UTBB-FDSOI FET B Awadhiya, S Yadav, A Acharya Silicon 15 (2), 937-942, 2023 | 3 | 2023 |
| Investigation of III-V Tunnel FETs for Analog Circuit Design AK Yadav, A Acharya 2021 Devices for Integrated Circuit (DevIC), 416-420, 2021 | 3 | 2021 |
| In-memory Computing based Boolean and logical Circuit Design using 8T SRAM C Yeswanth, A Acharya 2021 Devices for Integrated Circuit (DevIC), 430-434, 2021 | 3 | 2021 |
| Influences of Source/Drain Extension Region on Thermal Behavior of Stacked Nanosheet FET S Srivastava, S Panwar, M Shashidhara, L Chandra, N Mishra, A Acharya IEEE Transactions on Electron Devices, 2024 | 2 | 2024 |
| Challenges and future scope of gate-all-around (GAA) transistors: Physical insights of device-circuit interactions S Srivastava, A Acharya Device Circuit Co-Design Issues in FETs, 231-258, 2024 | 2 | 2024 |
| Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective S Srivastava, M Shashidhara, S Panwar, S Yadav, A Acharya Solid-State Electronics 208, 108758, 2023 | 2 | 2023 |
| Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight A Acharya, A Bulusu 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 2 | 2023 |
| 9T SRAM Cell for Computation-In-Memory Architectures: Proposal & Investigation AK Gupta, P Joshi, S Srivastava, S Panwar, RS Shekhawat, AS Kilak, ... 2023 IEEE Devices for Integrated Circuit (DevIC), 282-286, 2023 | 2 | 2023 |
Shobhit SrivastavaPhD Scholar | National Institute of Technology, Surat在 eced.svnit.ac.in 的电子邮件经过验证
