| Test set compaction algorithms for combinational circuits I Hamzaoglu, JH Patel Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 620 | 1998 |
| Reducing test application time for full scan embedded cores I Hamzaoglu, JH Patel Digest of Papers. Twenty-Ninth Annual International Symposium on Fault …, 1999 | 464 | 1999 |
| Scalable, distributed data mining-an agent architecture H Kargupta, I Hamzaoglu, B Stafford Proceedings Third International Conference on Knowledge Discovery and Data …, 1997 | 230 | 1997 |
| New techniques for deterministic test pattern generation I Hamzaoglu, JH Patel Journal of Electronic Testing 15, 63-73, 1999 | 201 | 1999 |
| Reducing test application time for built-in-self-test test pattern generators I Hamzaoglu, JH Patel VLSI Test Symposium, 2000. Proceedings. 18th IEEE, 369-375, 2000 | 82 | 2000 |
| A high performance deblocking filter hardware for high efficiency video coding E Ozcan, Y Adibelli, I Hamzaoglu IEEE Transactions on Consumer Electronics 59 (3), 714-720, 2013 | 69 | 2013 |
| A high performance and low energy intra prediction hardware for high efficiency video coding E Kalali, Y Adibelli, I Hamzaoglu 22nd International Conference on Field Programmable Logic and Applications …, 2012 | 58 | 2012 |
| High performance 2D transform hardware for future video coding AC Mert, E Kalali, I Hamzaoglu IEEE Transactions on Consumer Electronics 63 (2), 117-125, 2017 | 53 | 2017 |
| A computation and energy reduction technique for HEVC discrete cosine transform E Kalali, AC Mert, I Hamzaoglu IEEE Transactions on Consumer Electronics 62 (2), 166-174, 2016 | 52 | 2016 |
| Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation O Tasdizen, A Akin, H Kukner, I Hamzaoglu IEEE Transactions on Consumer Electronics 55 (3), 1645-1653, 2009 | 50 | 2009 |
| An efficient hardware architecture for H. 264 intra prediction algorithm E Sahin, I Hamzaoglu Proceedings of the conference on Design, automation and test in Europe, 183-188, 2007 | 50 | 2007 |
| Low power H. 264 deblocking filter hardware implementations M Parlak, I Hamzaoglu IEEE Transactions on Consumer Electronics 54 (2), 808-816, 2008 | 48 | 2008 |
| Compact two-pattern test set generation for combinational and full scan circuits I Hamzaoglu, JH Patel Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998 | 48 | 1998 |
| Efficient hardware implementations of low bit depth motion estimation algorithms A Celebi, O Urhan, I Hamzaoglu, S Erturk IEEE Signal Processing Letters 16 (6), 513-516, 2009 | 46 | 2009 |
| A low energy HEVC inverse transform hardware E Kalali, E Ozcan, OM Yalcinkaya, I Hamzaoglu IEEE Transactions on Consumer Electronics 60 (4), 754-761, 2014 | 45 | 2014 |
| A novel computational complexity and power reduction technique for H. 264 intra prediction M Parlak, Y Adibelli, I Hamzaoglu IEEE Transactions on Consumer Electronics 54 (4), 2006-2014, 2008 | 42 | 2008 |
| A low energy HEVC sub-pixel interpolation hardware E Kalali, I Hamzaoglu 2014 IEEE International Conference on Image Processing (ICIP), 1218-1222, 2014 | 38 | 2014 |
| An adaptive true motion estimation algorithm for frame rate conversion of high definition video and its hardware implementations M Çetin, İ Hamzaoğlu IEEE Transactions on Consumer Electronics 57 (2), 923-931, 2011 | 37 | 2011 |
| An efficient hardware architecture for quarter-pixel accurate H. 264 motion estimation S Oktem, I Hamzaoglu 10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007 | 36 | 2007 |
| A high performance hardware architecture for an SAD reuse based hierarchical motion estimation algorithm for H. 264 video coding S Yalcin, HF Ates, I Hamzaoglu International Conference on Field Programmable Logic and Applications, 2005 …, 2005 | 36 | 2005 |
