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Pin Su
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引用次数
年份
BSIM4 gate leakage model including source-drain partition
KM Cao, WC Lee, W Liu, X Jin, P Su, SKH Fung, JX An, B Yu, C Hu
International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000
2782000
Analysis of single-trap-induced random telegraph noise and its interaction with work function variation for tunnel FET
ML Fan, VPH Hu, YN Chen, P Su, CT Chuang
IEEE transactions on electron devices 60 (6), 2038-2044, 2013
672013
Analysis of single-trap-induced random telegraph noise on FinFET devices, 6T SRAM cell, and logic circuits
ML Fan, VPH Hu, YN Chen, P Su, CT Chuang
IEEE Transactions on Electron Devices 59 (8), 2227-2234, 2012
642012
On the body-source built-in potential lowering of SOI MOSFETs
P Su, SKH Fung, PW Wyatt, H Wan, AM Niknejad, M Chan, C Hu
IEEE Electron Device Letters 24 (2), 90-92, 2003
642003
Variability analysis for ferroelectric FET nonvolatile memories considering random ferroelectric-dielectric phase distribution
YS Liu, P Su
IEEE Electron Device Letters 41 (3), 369-372, 2020
632020
Investigation and comparison of work function variation for FinFET and UTB SOI devices using a Voronoi approach
SH Chou, ML Fan, P Su
IEEE transactions on electron devices 60 (4), 1485-1489, 2013
602013
Evaluation of stability, performance of ultra-low voltage MOSFET, TFET, and mixed TFET-MOSFET SRAM cell with write-assist circuits
YN Chen, ML Fan, VPH Hu, P Su, CT Chuang
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4 (4 …, 2014
582014
Influence of surface excitations on electrons elastically backscattered from copper and silver surfaces
YF Chen, P Su, CM Kwei, CJ Tung
Physical Review B 50 (23), 17547, 1994
571994
Comparison of 4T and 6T FinFET SRAM cells for subthreshold operation considering variability—A model-based approach
ML Fan, YS Wu, VPH Hu, CY Hsieh, P Su, CT Chuang
IEEE transactions on electron devices 58 (3), 609-616, 2011
522011
Investigation of cell stability and write ability of FinFET subthreshold SRAM using analytical SNM model
ML Fan, YS Wu, VPH Hu, P Su, CT Chuang
IEEE Transactions on Electron Devices 57 (6), 1375-1381, 2010
522010
Short-channel effects in 2D negative-capacitance field-effect transistors
WX You, CP Tsai, P Su
IEEE transactions on Electron Devices 65 (4), 1604-1610, 2018
502018
Independently-controlled-gate FinFET Schmitt trigger sub-threshold SRAMs
CY Hsieh, ML Fan, VPH Hu, P Su, CT Chuang
IEEE Transactions on very large scale integration (VLSI) systems 20 (7 …, 2011
502011
Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs
M Chan, P Su, H Wan, CH Lin, SKH Fung, AM Niknejad, C Hu, PK Ko
Solid-State Electronics 48 (6), 969-978, 2004
492004
A thermal activation view of low voltage impact ionization in MOSFETs
P Su, K Goto, T Sugii, C Hu
IEEE Electron Device Letters 23 (9), 550-552, 2002
472002
Design space exploration considering back-gate biasing effects for 2D negative-capacitance field-effect transistors
WX You, P Su
IEEE Transactions on Electron Devices 64 (8), 3476-3481, 2017
462017
Analytical quantum-confinement model for short-channel gate-all-around MOSFETs under subthreshold region
YS Wu, P Su
IEEE Transactions on Electron Devices 56 (11), 2720-2725, 2009
462009
BSIMPD: A partial-depletion SOI MOSFET model for deep-submicron CMOS designs
P Su, SKH Fung, S Tang, F Assaderaghi, C Hu
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No …, 2000
462000
Design and analysis of robust tunneling FET SRAM
YN Chen, ML Fan, VPH Hu, P Su, CT Chuang
IEEE transactions on electron devices 60 (3), 1092-1098, 2013
442013
FinFET SRAM cell optimization considering temporal variability due to NBTI/PBTI, surface orientation and various gate dielectrics
VPH Hu, ML Fan, CY Hsieh, P Su, CT Chuang
IEEE Transactions on Electron Devices 58 (3), 805-811, 2011
412011
Sensitivity of gate-all-around nanowire MOSFETs to process variations—A comparison with multigate MOSFETs
YS Wu, P Su
IEEE transactions on electron devices 55 (11), 3042-3047, 2008
412008
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