| Mitigation of Denial of Service Attack with Hardware Trojans in NoC Architecture T Boraten, A Kodi 30th IEEE International Parallel and Distributed Processing Symposium (IPDPS'16), 2016 | 67 | 2016 |
| Packet security with path sensitization for NoCs T Boraten, AK Kodi 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 60 | 2016 |
| Secure model checkers for network-on-chip (NoC) architectures T Boraten, D DiTomaso, AK Kodi Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 45-50, 2016 | 42 | 2016 |
| Dynamic Error Mitigation in NoCs using Intelligent Prediction Techniques D DiTomaso, T Boraten, A Kodi, A Louri 49th ACM/IEEE International Symposium on Microarchitecture (MICRO-49 …, 2016 | 40 | 2016 |
| Mitigation of Hardware Trojan based Denial-of-Service attack for secure NoCs T Boraten, A Kodi Journal of Parallel and Distributed Computing 111, 24-38, 2018 | 37 | 2018 |
| Securing NoCs against Timing Attacks with Non-Interference Based Adaptive Routing T Boraten, AK Kodi 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018), 2018 | 32 | 2018 |
| Runtime techniques to mitigate soft errors in network-on-chip (NoC) architectures T Boraten, AK Kodi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 25 | 2017 |
| Energy-efficient runtime adaptive scrubbing in fault-tolerant network-on-chips (nocs) architectures T Boraten, A Kodi 2013 IEEE 31st International Conference on Computer Design (ICCD), 264-271, 2013 | 12 | 2013 |
| Packet security with path sensitization for nocs. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) T Boraten, AK Kodi IEEE, 1136ś1139, 2016 | 9 | 2016 |
| A Research Retrospective on AMD's Exascale Computing Journey GH Loh, MJ Schulte, M Ignatowski, V Adhinarayanan, S Aga, D Aguren, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 7 | 2023 |
| Evaluation of fault tolerant channel buffers for improving reliability in NoCs D DiTomaso, T Boraten, A Kodi, A Louri 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 5 | 2012 |
| Hardware Security Threat and Mitigation Techniques for Network-on-Chips TH Boraten Ohio University, 2020 | 4 | 2020 |
| Runtime Adaptive Scrubbing in Fault-Tolerant Network-on-Chips (NoC) Architectures TH Boraten Ohio University, 2014 | 1 | 2014 |
| Condensed Coherence Directory Entries for Processing-in-Memory TH Boraten, V Agrawal, MW Boyer US Patent App. 18/146,904, 2024 | | 2024 |
| Semiconductor chip stack with locking through vias T Boraten US Patent 11,837,527, 2023 | | 2023 |
| A Method and Apparatus to lock TSVs for stacked ICs T Boraten US Patent US-11837527-B2, 2023 | | 2023 |
Avinash KaranthProfessor Ohio University在 ohio.edu 的电子邮件经过验证
Avinash KaranthProfessor Ohio University在 ohio.edu 的电子邮件经过验证