| 16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced … J Kim, H Yoon, Y Lim, Y Lee, Y Cho, T Seong, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 258-260, 2019 | 68 | 2019 |
| A low-integrated-phase-noise 27–30-GHz injection-locked frequency multiplier with an ultra-low-power frequency-tracking loop for mm-wave-band 5G transceivers S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi IEEE Journal of Solid-State Circuits 53 (2), 375-388, 2017 | 63 | 2017 |
| A− 31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection … H Yoon, J Kim, S Park, Y Lim, Y Lee, J Bang, K Lim, J Choi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 366-368, 2018 | 54 | 2018 |
| An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators J Kim, Y Lim, H Yoon, Y Lee, H Park, Y Cho, T Seong, J Choi IEEE Journal of Solid-State Circuits 54 (12), 3466-3477, 2019 | 37 | 2019 |
| 19.2 A PVT-robust− 39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase … S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi 2017 IEEE International Solid-State Circuits Conference (ISSCC), 324-325, 2017 | 36 | 2017 |
| 17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power … Y Lim, J Kim, Y Jo, J Bang, S Yoo, H Park, H Yoon, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 280-282, 2020 | 21 | 2020 |
| A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier Y Jo, J Kim, Y Shin, H Park, C Hwang, Y Lim, J Choi IEEE Journal of Solid-State Circuits, 2023 | 11 | 2023 |
| A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier Y Jo, J Kim, Y Shin, C Hwang, H Park, J Choi 2023 IEEE International Solid-State Circuits Conference (ISSCC), 1-3, 2023 | 10 | 2023 |
| 32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique J Kim, Y Jo, Y Lim, T Seong, H Park, S Yoo, Y Lee, S Choi, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 448-450, 2021 | 9 | 2021 |
| A wide-lock-in-range and low-jitter 12–14.5 GHz SSPLL using a low-power frequency-disturbance-detecting and correcting loop Y Lim, J Kim, Y Jo, J Bang, J Choi IEEE Journal of Solid-State Circuits 57 (2), 480-491, 2021 | 8 | 2021 |
| A 0.1–1.5-GHz wide harmonic-locking-free delay-locked loop using an exponential DAC S Park, J Kim, C Hwang, H Park, S Yoo, T Seong, J Choi IEEE Microwave and Wireless Components Letters 29 (8), 548-550, 2019 | 8 | 2019 |
| A 0.0084-mV-FOM, fast-transient and low-power external-clock-less digital LDO using a gear-shifting comparator for the wide-range adaptive sampling frequency J Bang, S Choi, S Yoo, J Lee, J Kim, J Choi ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | 7 | 2021 |
| A 12.8–15.0-GHz Low-Jitter Fractional- Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation J Kim, Y Jo, H Park, T Seong, Y Lim, J Choi IEEE Journal of Solid-State Circuits, 2023 | 2 | 2023 |
| 28.5 A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed … Y Shin, Y Jo, J Kim, J Lee, J Kim, J Choi 2023 IEEE International Solid-State Circuits Conference (ISSCC), 408-410, 2023 | 2 | 2023 |
| Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 303-304, 2018 | 1 | 2018 |
| 10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique Y Shin, J Lee, J Kim, Y Jo, J Choi 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 196-198, 2024 | | 2024 |
| An Ultra-Low Integrated-Phase-Noise 28-GHz LO Generator for 5G Transceivers Supporting Multiple Frequency Bands H Yoon, S Park, J Kim, J Choi 2022 IEEE International Symposium on Radio-Frequency Integration Technology …, 2022 | | 2022 |
Jaehyouk ChoiAssociate Professor of Seoul National University在 snu.ac.kr 的电子邮件经过验证
