| Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI F Assaderaghi, D Sinitsky, SA Parke, J Bokor, PK Ko, C Hu IEEE Transactions on Electron Devices 44 (3), 414-422, 1997 | 1165* | 1997 |
| SOI FET design to reduce transient bipolar current MMA Pelella, F Assaderaghi, LF Wagner Jr US Patent 5,770,881, 1998 | 279 | 1998 |
| Mixed memory integration with NVRAM, DRAM and SRAM cell structures on same substrate F Assaderaghi, LLC Hsu, JA Mandelman US Patent 6,424,011, 2002 | 245 | 2002 |
| Two-device memory cell on SOI for merged logic and memory applications F Assaderaghi, B Davari, LL Hsu, JA Mandelman, GG Shahidi US Patent 5,784,311, 1998 | 215 | 1998 |
| Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure LLC Hsu, JA Mandelman, F Assaderaghi US Patent 6,232,173, 2001 | 208 | 2001 |
| T-Ram array having a planar cell structure and method for fabricating the same LL Hsu, RV Joshi, F Assaderaghi US Patent 6,552,398, 2003 | 203 | 2003 |
| A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation F Assaderaghi, S Parke, D Sinitsky, J Bokor, PK Ko, C Hu IEEE Electron Device Letters 15 (12), 510-512, 1994 | 164 | 1994 |
| Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET C Wann, F Assaderaghi, R Dennard, C Hu, G Shahidi, Y Taur International Electron Devices Meeting. Technical Digest, 113-116, 1996 | 156 | 1996 |
| Method and system for improving the performance on SOI memory arrays in an SRAM architecture system LL Hsu, RV Joshi, F Assaderaghi, MJ Saccamango US Patent 6,549,450, 2003 | 151 | 2003 |
| Double SOI device with recess etch and epitaxy F Assaderaghi, TC Chen, KP Muller, EJ Nowak, DK Sadana, GG Shahidi US Patent 6,432,754, 2002 | 138 | 2002 |
| IEDM Technical Digest J Chen, S Parke, J King, F Assaderaghi, P Ko, C Hu IEEE International Electron Devices Meeting (San Francisco, CA, 2004), 733, 1992 | 132 | 1992 |
| Dispensing device PT Price, S Bley, B Sams US Patent 6,770,056, 2004 | 129 | 2004 |
| Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications F Assaderaghi, LLC Hsu, JA Mandelman, GG Shahidi, SH Voldman US Patent 5,811,857, 1998 | 123 | 1998 |
| The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta J Chen, F Assaderaghi, PK Ko, C Hu IEEE electron device letters 13 (11), 572-574, 1992 | 108 | 1992 |
| Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure LLC Hsu, JA Mandelman, F Assaderaghi US Patent 5,880,991, 1999 | 101 | 1999 |
| Partially-depleted SOI technology for digital logic GG Shahidi, A Ajmera, F Assaderaghi, RJ Bolam, E Leobandung, ... 1999 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1999 | 96 | 1999 |
| Integrated circuit with built-in heating circuitry to reverse operational degeneration G Bronner, BS Haukness, F Assaderaghi, MD Kellam, M Horowitz US Patent App. 12/516,499, 2010 | 92 | 2010 |
| Body contact MOSFET A Bryant, PE Cottrell, JJ Ellis-Monaghan, RJ Gauthier Jr, EJ Nowak, ... US Patent 6,677,645, 2004 | 91 | 2004 |
| T-RAM array having a planar cell structure and method for fabricating the same LL Hsu, RV Joshi, F Assaderaghi, D Moy, W Rausch, J Culp US Patent 6,713,791, 2004 | 90 | 2004 |
| A 16 Gb/s/link, 64 GB/s bidirectional asymmetric memory interface H Lee, KYK Chang, JH Chun, T Wu, Y Frans, B Leibowitz, N Nguyen, ... IEEE Journal of Solid-State Circuits 44 (4), 1235-1247, 2009 | 78 | 2009 |
chenming huUniversity of California, Berkeley在 eecs.berkeley.edu 的电子邮件经过验证
