| Parameter variations and impact on circuits and microarchitecture S Borkar, T Karnik, S Narendra, J Tschanz, A Keshavarzi, V De Proceedings of the 40th annual Design Automation Conference, 338-342, 2003 | 1900 | 2003 |
| A 0.45–1 V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS R Jain, BM Geuskens, ST Kim, MM Khellah, J Kulkarni, JW Tschanz, V De IEEE Journal of Solid-State Circuits 49 (4), 917-927, 2014 | 114 | 2014 |
| A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14-nm tri-gate CMOS HK Krishnamurthy, V Vaidya, P Kumar, R Jain, S Weng, ST Kim, ... IEEE Journal of Solid-State Circuits 53 (1), 8-19, 2017 | 101 | 2017 |
| Variation-tolerant circuits: circuit solutions and techniques J Tschanz, K Bowman, V De Proceedings of the 42nd Annual Design Automation Conference, 762-763, 2005 | 88 | 2005 |
| PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction A Raychowdhury, B Geuskens, J Kulkarni, J Tschanz, K Bowman, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 352-353, 2010 | 83 | 2010 |
| Numerical analysis of domain wall propagation for dense memory arrays C Augustine, A Raychowdhury, B Behin-Aein, S Srinivasan, J Tschanz, ... 2011 International Electron Devices Meeting, 17.6. 1-17.6. 4, 2011 | 58 | 2011 |
| Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays C Augustine, A Raychowdhury, D Somasekhar, J Tschanz, K Roy, VK De 2010 International Electron Devices Meeting, 22.7. 1-22.7. 4, 2010 | 52 | 2010 |
| A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS R Jain, B Geuskens, M Khellah, S Kim, J Kulkarni, J Tschanz, V De 2013 Symposium on VLSI Circuits, C174-C175, 2013 | 44 | 2013 |
| Design for resilience to soft errors and variations M Zhang, TM Mak, J Tschanz, KS Kim, N Seifert, D Lu 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 23-28, 2007 | 41 | 2007 |
| 8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation ST Kim, YC Shih, K Mazumdar, R Jain, JF Ryan, C Tokunaga, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 39 | 2015 |
| Dual-VCC 8T-bitcell SRAM array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range J Kulkarni, M Khellah, J Tschanz, B Geuskens, R Jain, S Kim, V De 2013 Symposium on VLSI Technology, C126-C127, 2013 | 38 | 2013 |
| A 22nm dynamically adaptive clock distribution for voltage droop tolerance KA Bowman, C Tokunaga, T Karnik, VK De, JW Tschanz 2012 Symposium on VLSI Circuits (VLSIC), 94-95, 2012 | 21 | 2012 |
| Characterization of inverse temperature dependence in logic circuits M Cho, M Khellah, K Chae, K Ahmed, J Tschanz, S Mukhopadhyay Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 16 | 2012 |
| Error detection and correction in microprocessor core and memory due to fast dynamic voltage droops A Raychowdhury, J Tschanz, K Bowman, SL Lu, P Aseron, M Khellah, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (3 …, 2011 | 14 | 2011 |
| Reliability challenges in nano-CMOS Design Y Cao, P Bose, J Tschanz IEEE Design & Test of Computers, 6-7, 2009 | 13 | 2009 |
| Minimum supply voltage for sequential logic circuits in a 22nm technology CH Chen, K Bowman, C Augustine, Z Zhang, J Tschanz International Symposium on Low Power Electronics and Design (ISLPED), 181-186, 2013 | 12 | 2013 |
| Guest editors' introduction: Reliability challenges in nano-cmos design Y Cao, J Tschanz, P Bose IEEE Design & Test of Computers 26 (6), 6-7, 2009 | 11 | 2009 |
| A low-power, reconfigurable adaptive equalizer architecture J Tschanz, NR Shanbhag Conference Record of the Thirty-Third Asilomar Conference on Signals …, 1999 | 11 | 1999 |
| A 0.05 pJ/pixel 70fps FHD 1Meps event-driven visual data processing unit S Paul, T Majumder, C Augustine, AF Malavasi, S Usirikayala, R Kumar, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 8 | 2020 |
| Low swing and column multiplexed bitline techniques for low-vmin, noise-tolerant, high-density, 1R1W 8T-bitcell SRAM in 10nm FinFET CMOS JP Kulkarni, A Malavasi, C Augustine, C Tokunaga, J Tschanz, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 4 | 2020 |
