| Digital phase locked loop with dithering K Waheed, M Sheba, RB Staszewski, S Vamvakos US Patent 7,786,913, 2010 | 80 | 2010 |
| On the departure process of a leaky bucket system with long-range dependent input traffic S Vamvakos, V Anantharam Queueing Systems 28, 191-214, 1998 | 56 | 1998 |
| Digital phase locked loop with dithering K Waheed, M Sheba, RB Staszewski, S Vamvakos US Patent 7,920,081, 2011 | 55 | 2011 |
| Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences K Waheed, RB Staszewski, F Dulger, MS Ullah, SD Vamvakos IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 2051-2060, 2011 | 43 | 2011 |
| 6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET E Groen, C Boecker, M Hossain, R Vu, S Vamvakos, H Lin, S Li, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 120-122, 2020 | 39 | 2020 |
| Noise analysis of time-to-digital converter in all-digital PLLs SD Vamvakos, RB Staszewski, M Sheba, K Waheed 2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and …, 2006 | 32 | 2006 |
| Digital phase locked loop with dithering K Waheed, M Sheba, RB Staszewski, S Vamvakos US Patent App. 13/038,885, 2011 | 28 | 2011 |
| ADC-DSP-based 10-to-112-Gb/s multi-standard receiver in 7-nm FinFET H Lin, C Boecker, M Hossain, S Tangirala, R Vu, SD Vamvakos, E Groen, ... IEEE Journal of Solid-State Circuits 56 (4), 1265-1277, 2021 | 21 | 2021 |
| PLL on-chip jitter measurement: Analysis and design S Vamvakos, V Stojanovic, J Zerbe, C Werner, D Draper, B Nikolic 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 73-74, 2006 | 19 | 2006 |
| Discrete-time, linear periodically time-variant phase-locked loop model for jitter analysis SD Vamvakos, V Stojanovic, B Nikolic IEEE Transactions on Circuits and Systems I: Regular Papers 58 (6), 1211-1224, 2011 | 18 | 2011 |
| 10-to-112-Gb/s DSP-DAC-based transmitter in 7-nm FinFET with flex clocking architecture E Groen, C Boecker, M Hossain, R Vu, SD Vamvakos, H Lin, S Li, ... IEEE Journal of Solid-State Circuits 56 (1), 30-42, 2020 | 14 | 2020 |
| A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications SD Vamvakos, CR Gauthier, C Rao, KR Canagasaby, P Choudhary, ... 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 14 | 2012 |
| Phase-locked loop architecture for adaptive jitter optimization SD Vamvakos, C Werner, B Nikolic 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 4, IV-161, 2004 | 14 | 2004 |
| A 4× 112 Gb/s ADC-DSP based multistandard receiver in 7nm FinFET H Lin, C Boecker, M Hossain, S Tangirala, R Vu, S Vamvakos, E Groen, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 12 | 2020 |
| A 8.125–15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop SD Vamvakos, C Boecker, E Groen, A Wang, S Desai, S Irwin, V Rao, ... Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 11 | 2014 |
| Modelling, parameter assessment and multiplexing analysis of bursty sources with hyper-exponentially distributed bursts N Mitrou, S Vamvakos, K Kontovasilis Computer networks and ISDN systems 27 (7), 1175-1192, 1995 | 9 | 1995 |
| Discrete-time, cyclostationary phase-locked loop model for jitter analysis SD Vamvakos, V Stojanovic, B Nikolic 2009 IEEE Custom Integrated Circuits Conference, 637-640, 2009 | 6 | 2009 |
| An intelligent RAM with serial I/Os B Kleveland, MJ Miller, RB David, J Patel, R Chopra, DK Sikdar, J Kumala, ... IEEE Micro 33 (6), 56-65, 2013 | 4 | 2013 |
| A 576 Mb DRAM with 16-channel 10.3125 Gbps Serial I/O and 14.5 ns Latency SD Vamvakos, B Kleveland, D Sikdar, BK Ahuja, H Lin, J Balachandran, ... 2012 Proceedings of the ESSCIRC (ESSCIRC), 458-461, 2012 | 3 | 2012 |
| Analysis, measurement and optimization of jitter in phase-locked loops SD Vamvakos University of California, Berkeley, 2005 | 2 | 2005 |
