| Pact: Parameterized clipping activation for quantized neural networks J Choi, Z Wang, S Venkataramani, PIJ Chuang, V Srinivasan, ... arXiv preprint arXiv:1805.06085, 2018 | 1019 | 2018 |
| Accurate and efficient 2-bit quantized neural networks J Choi, S Venkataramani, VV Srinivasan, K Gopalakrishnan, Z Wang, ... Proceedings of Machine Learning and Systems 1, 348-359, 2019 | 197 | 2019 |
| A scalable multi-TeraOPS deep learning processor core for AI trainina and inference B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ... 2018 IEEE symposium on VLSI circuits, 35-36, 2018 | 153 | 2018 |
| Bridging the accuracy gap for 2-bit quantized neural networks (qnn) J Choi, PIJ Chuang, Z Wang, S Venkataramani, V Srinivasan, ... arXiv preprint arXiv:1807.06964, 2018 | 82 | 2018 |
| Compensated-DNN: Energy efficient low-precision deep neural networks by compensating quantization errors S Jain, S Venkataramani, V Srinivasan, J Choi, P Chuang, L Chang Proceedings of the 55th annual design automation conference, 1-6, 2018 | 76 | 2018 |
| 26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection MS Floyd, PJ Restle, MA Sperling, P Owczarczyk, EJ Fluhr, J Friedrich, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 444-445, 2017 | 56 | 2017 |
| A low-power high-performance single-cycle tree-based 64-bit binary comparator P Chuang, D Li, M Sachdev IEEE Transactions on Circuits and Systems II: Express Briefs 59 (2), 108-112, 2012 | 50 | 2012 |
| Comparative analysis and study of metastability on high-performance flip-flops D Li, P Chuang, M Sachdev 2010 11th international symposium on quality electronic design (ISQED), 853-860, 2010 | 42 | 2010 |
| Constant delay logic style P Chuang, D Li, M Sachdev IEEE transactions on very large scale integration (VLSI) systems 21 (3), 554-565, 2012 | 41 | 2012 |
| A scalable multi-TeraOPS core for AI training and inference S Shukla, B Fleischer, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ... IEEE Solid-State Circuits Letters 1 (12), 217-220, 2018 | 33 | 2018 |
| A 167-ps 2.34-mW single-cycle 64-bit binary tree comparator with constant-delay logic in 65-nm CMOS I Pierce, J Chuang, M Sachdev, VC Gaudet IEEE Transactions on Circuits and Systems I: Regular Papers 61 (1), 160-171, 2013 | 32 | 2013 |
| One weight bitwidth to rule them all TW Chin, PIJ Chuang, V Chandra, D Marculescu Computer Vision–ECCV 2020 Workshops: Glasgow, UK, August 23–28, 2020 …, 2020 | 29 | 2020 |
| The 24-core POWER9 processor with adaptive clocking, 25-Gb/s accelerator links, and 16-Gb/s PCIe Gen4 C Gonzalez, M Floyd, E Fluhr, P Restle, D Dreps, M Sperling, R Rao, ... IEEE Journal of Solid-State Circuits 53 (1), 91-101, 2017 | 25 | 2017 |
| Span pointer networks for non-autoregressive task-oriented semantic parsing A Shrivastava, P Chuang, A Babu, S Desai, A Arora, A Zotov, A Aly arXiv preprint arXiv:2104.07275, 2021 | 24 | 2021 |
| Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor C Vezyrtzis, T Strach, I Pierce, J Chuang, P Lobo, R Rizzolo, T Webel, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 300-302, 2018 | 24 | 2018 |
| Viterbi-based pruning for sparse matrix with fixed and high index compression ratio D Lee, D Ahn, T Kim, PI Chuang, JJ Kim International Conference on Learning Representations, 2018 | 23 | 2018 |
| 26.2 Power supply noise in a 22nm z13™ microprocessor P Chuang, C Vezyrtzis, D Pathak, R Rizzolo, T Webel, T Strach, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 438-439, 2017 | 23* | 2017 |
| Design and analysis of metastable-hardened flip-flops in sub-threshold region D Li, I Pierce, J Chuang, D Nairn, M Sachdev IEEE/ACM International Symposium on Low Power Electronics and Design, 157-162, 2011 | 23 | 2011 |
| Design of a 64-bit low-energy high-performance adder using dynamic feedthrough logic P Chuang, D Li, M Sachdev 2009 IEEE International Symposium on Circuits and Systems, 3038-3041, 2009 | 21 | 2009 |
| Pact: Parameterized clipping activation for quantized neural networks. arXiv J Choi, Z Wang, S Venkataramani, PIJ Chuang, V Srinivasan, ... arXiv preprint arXiv:1805.06085, 2018 | 20 | 2018 |
