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Seyed Mohammad Reza Shahshahani
Seyed Mohammad Reza Shahshahani
Virgobit
在 sbu.ac.ir 的电子邮件经过验证 - 首页
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A high-performance scalable shared-memory SVD processor architecture based on Jacobi algorithm and Batcher’s sorting network
SMR Shahshahani, HR Mahdiani
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (6), 1912-1924, 2020
142020
A custom hardware CCA engine for real-time SSVEP-based BCI applications
R Karkon, SMR Shahshahani, HR Mahdiani
2020 20th International Symposium on Computer Architecture and Digital …, 2020
82020
FiCA: A Fixed-point Custom Architecture FastICA for Real-time and Latency-Sensitive Applications
SMR Shahshahani, HR Mahdiani
IEEE Transactions on Neural Systems and Rehabilitation Engineering, 2022
62022
A new IC designed inside capsule endoscope for detection of bleeding region
H Daryanavard, G Karimian, SMR Shahshahani
2010 17th Iranian Conference of Biomedical Engineering (ICBME), 1-4, 2010
22010
A New Pipeline Implementation of JPEG-LS Compression Algorithm for Capsule Endoscope Applications
H Daryanavard, G Karimian, SMR Shahshahani, HB Bahar
International Review on Computers and Software 5 (6), 635-642, 2010
2010
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