| SigRace: signature-based data race detection A Muzahid, D Suárez, S Qi, J Torrellas ACM SIGARCH Computer Architecture News 37 (3), 337-348, 2009 | 119 | 2009 |
| Methods and systems for detecting malware and attacks that target behavioral security mechanisms of a mobile device DS Garcia, R Gupta, A Gantman US Patent 9,357,397, 2016 | 62 | 2016 |
| Directed event signaling for multiprocessor systems DS Gracia, H Zhao, PM Ortego, GC Cascaval, J Xenidis US Patent 9,632,569, 2017 | 59 | 2017 |
| Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL MA Dávila Guzmán, R Nozal, R Gran Tejero, M Villarroya-Gaudó, ... The Journal of Supercomputing 75, 1732-1746, 2019 | 48 | 2019 |
| Software Configurations for Mobile Devices in a Collaborative Environment H Chao, DS Gracia, GC Cascaval US Patent App. 14/300,407, 2015 | 41 | 2015 |
| Concertina: Squeezing in cache content to operate at near-threshold voltage A Ferreron, D Suarez-Gracia, J Alastruey-Benede, T Monreal-Arnal, ... IEEE Transactions on Computers 65 (3), 755-769, 2015 | 32 | 2015 |
| Simultaneous multiprocessing in a software-defined heterogeneous FPGA J Nunez-Yanez, S Amiri, M Hosseinabady, A Rodríguez, R Asenjo, ... The Journal of Supercomputing 75, 4078-4095, 2019 | 30* | 2019 |
| Data management for multiple processing units using data transfer costs DS Gracia, T Kumar, A Natarajan, R Hastantram, GC Cascaval, H Zhao US Patent 9,733,978, 2017 | 27 | 2017 |
| Proactive resource management for parallel work-stealing processing systems H Zhao, DS Gracia, T Kumar US Patent 10,360,063, 2019 | 26 | 2019 |
| Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs A Rodríguez, A Navarro, R Asenjo, F Corbera, R Gran, D Suárez, ... Journal of Systems Architecture 98, 27-40, 2019 | 25 | 2019 |
| LP-NUCA: Networks-in-cache for high-performance low-power embedded processors DS Gracia, G Dimitrakopoulos, TM Arnal, MGH Katevenis, VV Yúfera IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (8 …, 2011 | 23 | 2011 |
| Parallel multiprocessing and scheduling on the heterogeneous Xeon+ FPGA platform A Rodríguez, A Navarro, R Asenjo, F Corbera, R Gran, D Suárez, ... The Journal of Supercomputing 76, 4645-4665, 2020 | 17 | 2020 |
| Automatic discovery of performance and energy pitfalls in html and css A Sampson, C Caşcaval, L Ceze, P Montesinos, DS Gracia 2012 IEEE International Symposium on Workload Characterization (IISWC), 82-83, 2012 | 17 | 2012 |
| Data-Driven Accelerator For Machine Learning And Raw Data Analysis B Robatmili, ML Badin, DS Gracia, GC Cascaval, N Islam US Patent App. 14/862,408, 2017 | 16 | 2017 |
| Analysis of network-on-chip topologies for cost-efficient chip multiprocessors M Ortín-Obón, D Suárez-Gracia, M Villarroya-Gaudó, C Izu, ... Microprocessors and Microsystems 42, 24-36, 2016 | 15 | 2016 |
| An aging-aware GPU register file design based on data redundancy A Valero, F Candel, D Suárez-Gracia, S Petit, J Sahuquillo IEEE Transactions on Computers 68 (1), 4-20, 2018 | 11 | 2018 |
| On the use of many-core Marvell ThunderX2 processor for HPC workloads V Soria-Pardos, A Armejach, D Suárez, M Moretó The Journal of Supercomputing 77, 3315-3338, 2021 | 10 | 2021 |
| Light NUCA: a proposal for bridging the inter-cache latency gap D Suárez, T Monreal Arnal, F Vallejo, JR Beivide Palacio, V Viñals Yufera Design, Automation and Test in Europe 2009, 530-535, 2009 | 10 | 2009 |
| A proposal to introduce power and energy notions in computer architecture laboratories AA Pérez, DS Gracia, VV Yúfera Proceedings of the 2007 workshop on Computer architecture education, 52-57, 2007 | 9 | 2007 |
| An analytical model of memory-bound applications compiled with high level synthesis MA Dávila-Guzmán, RG Tejero, M Villarroya-Gaudó, DS Gracia 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020 | 8 | 2020 |
Rubén Gran TejeroUniversidad de Zaragoza在 unizar.es 的电子邮件经过验证
