| Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using heterodielectric BOX S Sahay, MJ Kumar IEEE transactions on electron devices 62 (11), 3882-3886, 2015 | 133 | 2015 |
| Nanotube junctionless FET: proposal, design, and investigation S Sahay, MJ Kumar IEEE Transactions on Electron Devices 64 (4), 1851-1856, 2017 | 107 | 2017 |
| Junctionless field-effect transistors: design, modeling, and simulation S Sahay, MJ Kumar John Wiley & Sons, 2019 | 100 | 2019 |
| Insight into lateral band-to-band-tunneling in nanowire junctionless FETs S Sahay, MJ Kumar IEEE Transactions on Electron Devices 63 (10), 4138-4142, 2016 | 100 | 2016 |
| Diameter dependence of leakage current in nanowire junctionless field effect transistors S Sahay, MJ Kumar IEEE Transactions on Electron Devices 64 (3), 1330-1335, 2017 | 88 | 2017 |
| Controlling L-BTBT and volume depletion in nanowire JLFETs using core–shell architecture S Sahay, MJ Kumar IEEE Transactions on Electron Devices 63 (9), 3790-3794, 2016 | 80 | 2016 |
| Realizing efficient volume depletion in SOI junctionless FETs S Sahay, MJ Kumar IEEE Journal of the Electron Devices Society 4 (3), 110-115, 2016 | 73 | 2016 |
| Spacer design guidelines for nanowire FETs from gate-induced drain leakage perspective S Sahay, MJ Kumar IEEE Transactions on Electron Devices 64 (7), 3007-3015, 2017 | 67 | 2017 |
| Physical insights into the nature of gate-induced drain leakage in ultrashort channel nanowire FETs S Sahay, MJ Kumar IEEE Transactions on Electron Devices 64 (6), 2604-2610, 2017 | 63 | 2017 |
| Controlling BTBT-induced parasitic BJT action in junctionless FETs using a hybrid channel MJ Kumar, S Sahay IEEE Transactions on Electron Devices 63 (8), 3350-3353, 2016 | 63 | 2016 |
| Nanotube tunneling FET with a core source for ultrasteep subthreshold swing: A simulation study G Musalgaonkar, S Sahay, RS Saxena, MJ Kumar IEEE Transactions on Electron Devices 66 (10), 4425-4432, 2019 | 59 | 2019 |
| A novel gate-stack-engineered nanowire FET for scaling to the sub-10-nm regime S Sahay, MJ Kumar IEEE Transactions on Electron Devices 63 (12), 5055-5059, 2016 | 51 | 2016 |
| A line tunneling field-effect transistor based on misaligned core–shell gate architecture in emerging nanotube FETs G Musalgaonkar, S Sahay, RS Saxena, MJ Kumar IEEE Transactions on Electron Devices 66 (6), 2809-2816, 2019 | 50 | 2019 |
| Symmetric operation in an extended back gate JLFET for scaling to the 5-nm regime considering quantum confinement effects S Sahay, MJ Kumar IEEE Transactions on Electron Devices 64 (1), 21-27, 2016 | 41 | 2016 |
| Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits S Sahay, M Suri Semiconductor Science and Technology 32 (12), 123001, 2017 | 36 | 2017 |
| 3D-aCortex: An ultra-compact energy-efficient neurocomputing platform based on commercial 3D-NAND flash memories M Bavandpour, S Sahay, MR Mahmoodi, DB Strukov Neuromorphic Computing and Engineering 1 (1), 014001, 2021 | 35 | 2021 |
| Controlling L-BTBT in emerging nanotube FETs using dual-material gate AK Jain, S Sahay, MJ Kumar IEEE Journal of the Electron Devices Society 6, 611-621, 2018 | 34 | 2018 |
| Comprehensive analysis of gate-induced drain leakage in emerging FET architectures: Nanotube FETs versus nanowire FETs S Sahay, MJ Kumar IEEE Access 5, 18918-18926, 2017 | 34 | 2017 |
| A behavioral compact model for static characteristics of 3D NAND flash memory S Sahay, D Strukov IEEE Electron Device Letters 40 (4), 558-561, 2019 | 28 | 2019 |
| Efficient mixed-signal neurocomputing via successive integration and rescaling M Bavandpour, S Sahay, MR Mahmoodi, D Strukov IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (3), 823-827, 2019 | 27 | 2019 |
Mamidala Jagadesh Kumar.Indian Institute of Technology Delhi; Chairman, UGC在 ee.iitd.ac.in 的电子邮件经过验证
