| Generation and manipulation of realistic signals for circuit and system verification TM Hollis US Patent 7,720,654, 2010 | 204 | 2010 |
| Matrix modeling of parallel data structures to facilitate data encoding and/or jittery signal generation TM Hollis US Patent 7,899,653, 2011 | 118 | 2011 |
| Mitigating ISI through self-calibrating continuous-time equalization TM Hollis, DJ Comer, DT Comer IEEE Transactions on Circuits and Systems I: Regular Papers 53 (10), 2234-2245, 2006 | 82 | 2006 |
| Circuit and Modeling Solutions for High-Speed Chip-To-Chip Communication TM Hollis Brigham Young University, 2007 | 63 | 2007 |
| Inter-symbol Interference in Manchester Encoded Data TM Hollis Oct, 2006 | 61 | 2006 |
| Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures T Hollis, RE Greeff US Patent 10,365,833, 2019 | 58 | 2019 |
| Data bus inversion in high-speed memory applications TM Hollis IEEE Transactions on Circuits and Systems II: Express Briefs 56 (4), 300-304, 2009 | 55 | 2009 |
| Data bus inversion apparatus, systems, and methods T Hollis US Patent 7,616,133, 2009 | 51 | 2009 |
| Optimization of MOS amplifier performance through channel length and inversion level selection TM Hollis, DJ Comer, DT Comer IEEE Transactions on Circuits and Systems II: Express Briefs 52 (9), 545-549, 2005 | 50 | 2005 |
| Self-calibrating continuous-time equalization TM Hollis US Patent 8,406,356, 2013 | 46 | 2013 |
| An 8-Gb GDDR6X DRAM achieving 22 Gb/s/pin with single-ended PAM-4 signaling TM Hollis, R Schneider, M Brox, T Hein, W Spirkl, M Bach, M Balakrishnan, ... IEEE Journal of Solid-State Circuits 57 (1), 224-235, 2021 | 44 | 2021 |
| Multi-level signaling in memory with wide system interface TM Hollis, M Balb, R Ebert US Patent 10,425,260, 2019 | 44 | 2019 |
| Data bus inversion usable in a memory system TM Hollis US Patent 9,116,828, 2015 | 43 | 2015 |
| Mixed-mode signaling TM Hollis US Patent 8,363,707, 2013 | 43 | 2013 |
| Multi-level signaling for low power, short channel applications TM Hollis US Patent 8,026,740, 2011 | 40 | 2011 |
| Data encoding using spare channels in a memory system TM Hollis US Patent 9,087,025, 2015 | 39 | 2015 |
| Methods and apparatuses for low-power multi-level encoded signals TM Hollis US Patent 8,854,236, 2014 | 39 | 2014 |
| Fractional-rate decision feedback equalization useful in a data transmission system TM Hollis US Patent 7,936,812, 2011 | 37 | 2011 |
| Output driver circuit with auto-equalization based on drive strength calibration TM Hollis, TC Bryan, M Wayland US Patent 9,337,807, 2016 | 36 | 2016 |
| Balanced data bus inversion TM Hollis US Patent 7,701,368, 2010 | 36 | 2010 |
