| Maximum-weight stable sets and safe lower bounds for graph coloring S Held, W Cook, EC Sewell Mathematical Programming Computation 4 (4), 363-381, 2012 | 107 | 2012 |
| Clock scheduling and clocktree construction for high performance ASICs S Held, B Korte, J Maßberg, M Ringe, J Vygen ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 75 | 2003 |
| Combinatorial optimization in VLSI design S Held, B Korte, D Rautenbach, J Vygen Combinatorial Optimization, 33-96, 2011 | 50 | 2011 |
| Global routing with timing constraints S Held, D Müller, D Rotter, R Scheifele, V Traub, J Vygen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 38 | 2017 |
| Gate sizing for large cell-based designs S Held 2009 Design, Automation & Test in Europe Conference & Exhibition, 827-832, 2009 | 31 | 2009 |
| Shallow-light Steiner arborescences with vertex delays S Held, D Rotter International Conference on Integer Programming and Combinatorial …, 2013 | 24 | 2013 |
| Provably fast and near-optimum gate sizing S Daboul, N Hähnle, S Held, U Schorr IEEE transactions on computer-aided design of integrated circuits and …, 2018 | 23 | 2018 |
| Safe lower bounds for graph coloring S Held, W Cook, EC Sewell Integer Programming and Combinatoral Optimization: 15th International …, 2011 | 23 | 2011 |
| Constrained local search for last-mile routing W Cook, S Held, K Helsgaun Transportation Science 58 (1), 12-26, 2024 | 22 | 2024 |
| The repeater tree construction problem C Bartoschek, S Held, J Maßberg, D Rautenbach, J Vygen Information Processing Letters 110 (24), 1079-1083, 2010 | 20 | 2010 |
| Efficient generation of short and fast repeater tree topologies C Bartoschek, S Held, D Rautenbach, J Vygen Proceedings of the 2006 international symposium on Physical design, 120-127, 2006 | 20 | 2006 |
| A fast algorithm for rectilinear Steiner trees with length restrictions on obstacles S Held, ST Spirkl Proceedings of the 2014 on International symposium on physical design, 37-44, 2014 | 17 | 2014 |
| Timing closure in chip design S Held Universitäts-und Landesbibliothek Bonn, 2008 | 16 | 2008 |
| Local search algorithms for timing-driven placement under arbitrary delay models A Bock, S Held, N Kämmerling, U Schorr Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 14 | 2015 |
| Post-routing latch optimization for timing closure S Held, U Schorr Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 14 | 2014 |
| Binary adder circuits of asymptotically minimum depth, linear size, and fan-out two S Held, ST Spirkl ACM Transactions on Algorithms (TALG) 14 (1), 1-18, 2017 | 12 | 2017 |
| Fast prefix adders for non-uniform input arrival times S Held, S Spirkl Algorithmica 77, 287-308, 2017 | 12 | 2017 |
| Fast buffering for optimizing worst slack and resource consumption in repeater trees C Bartoschek, S Held, D Rautenbach, J Vygen Proceedings of the 2009 international symposium on Physical design, 43-50, 2009 | 11 | 2009 |
| Global routing with inherent static timing constraints S Held, D Müller, D Rotter, V Traub, J Vygen 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 102-109, 2015 | 10 | 2015 |
| Routing System C Beckmann, K Pientka, L Fischer, L Krämer, J Vygen, S Held, D Müller US Patent App. 15/648,630, 2019 | 7 | 2019 |
Jens VygenProfessor of Discrete Mathematics, University of Bonn在 or.uni-bonn.de 的电子邮件经过验证
