| Advances, challenges and opportunities in 3D CMOS sequential integration P Batude, M Vinet, B Previtali, C Tabone, C Xu, J Mazurier, O Weber, ... 2011 International Electron Devices Meeting, 7.3. 1-7.3. 4, 2011 | 397 | 2011 |
| The EPFL combinational benchmark suite L Amarú, PE Gaillardon, G De Micheli Proceedings of the 24th International Workshop on Logic & Synthesis (IWLS), 2015 | 374 | 2015 |
| 3-D sequential integration: A key enabling technology for heterogeneous co-integration of new function with CMOS P Batude, T Ernst, J Arcamone, G Arndt, P Coudrain, PE Gaillardon IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (4 …, 2012 | 353 | 2012 |
| Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs M De Marchi, D Sacchetto, S Frache, J Zhang, PE Gaillardon, Y Leblebici, ... 2012 International Electron Devices Meeting, 8.4. 1-8.4. 4, 2012 | 323 | 2012 |
| Majority-inverter graph: A new paradigm for logic optimization L Amaru, PE Gaillardon, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 236 | 2015 |
| Can we go towards true 3-D architectures? PE Gaillardon, H Ben-Jamaa, PH Morel, JP Noël, F Clermidy, I O'Connor Proceedings of the 48th Design Automation Conference, 282-283, 2011 | 228 | 2011 |
| Majority-inverter graph: A novel data-structure and algorithms for efficient logic optimization L Amarú, PE Gaillardon, G De Micheli Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 215 | 2014 |
| The programmable logic-in-memory (PLiM) computer PE Gaillardon, L Amarú, A Siemon, E Linn, R Waser, A Chattopadhyay, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 427-432, 2016 | 193 | 2016 |
| Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs M De Marchi, J Zhang, S Frache, D Sacchetto, PE Gaillardon, Y Leblebici, ... IEEE Electron Device Letters 35 (8), 880-882, 2014 | 125 | 2014 |
| Doping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors GV Resta, Y Balaji, D Lin, IP Radu, F Catthoor, PE Gaillardon, ... ACS nano 12 (7), 7039-7047, 2018 | 124 | 2018 |
| Top–down fabrication of gate-all-around vertically stacked silicon nanowire FETs with controllable polarity M De Marchi, D Sacchetto, J Zhang, S Frache, PE Gaillardon, Y Leblebici, ... IEEE transactions on Nanotechnology 13 (6), 1029-1038, 2014 | 110 | 2014 |
| Exact synthesis of majority-inverter graphs and its applications M Soeken, LG Amaru, PE Gaillardon, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 108 | 2017 |
| Emerging technology-based design of primitives for hardware security Y Bi, K Shamsi, JS Yuan, PE Gaillardon, GD Micheli, X Yin, XS Hu, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (1), 1-19, 2016 | 100 | 2016 |
| Polarity control in WSe2 double-gate transistors GV Resta, S Sutar, Y Balaji, D Lin, P Raghavan, I Radu, F Catthoor, ... Scientific reports 6 (1), 29448, 2016 | 94 | 2016 |
| Configurable circuits featuring dual-threshold-voltage design with three-independent-gate silicon nanowire FETs J Zhang, X Tang, PE Gaillardon, G De Micheli IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2851-2861, 2014 | 94 | 2014 |
| Fast logic synthesis for RRAM-based in-memory computing using majority-inverter graphs S Shirinzadeh, M Soeken, PE Gaillardon, R Drechsler 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 948-953, 2016 | 89 | 2016 |
| Polarity-controllable silicon nanowire transistors with dual threshold voltages J Zhang, M De Marchi, D Sacchetto, PE Gaillardon, Y Leblebici, ... IEEE Transactions on Electron Devices 61 (11), 3654-3660, 2014 | 86 | 2014 |
| Development of a calibration chamber to evaluate the performance of low-cost particulate matter sensors T Sayahi, D Kaufman, T Becnel, K Kaur, AE Butterfield, S Collingwood, ... Environmental Pollution 255, 113131, 2019 | 85 | 2019 |
| Spinalflow: An architecture and dataflow tailored for spiking neural networks S Narayanan, K Taht, R Balasubramonian, E Giacomin, PE Gaillardon 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 84 | 2020 |
| Memristive logic: A framework for evaluation and comparison J Reuben, R Ben-Hur, N Wald, N Talati, AH Ali, PE Gaillardon, ... 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 84 | 2017 |
