| Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system S Schmitt, J Klähn, G Bellec, A Grübl, M Guettler, A Hartel, S Hartmann, ... 2017 international joint conference on neural networks (IJCNN), 2227-2234, 2017 | 194 | 2017 |
| Pattern representation and recognition with accelerated analog neuromorphic systems MA Petrovici, S Schmitt, J Klähn, D Stöckel, A Schroeder, G Bellec, J Bill, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 23 | 2017 |
| Dedicated FPGA communication architecture and design for a large-scale neuromorphic system V Thanasoulis, J Partzsch, S Hartmann, C Mayr, R Schüffny 2012 19th IEEE International Conference on Electronics, Circuits, and …, 2012 | 12 | 2012 |
| Classification with deep neural networks on an accelerated analog neuromorphic system S Schmitt, J Klähn, G Bellec, A Grübl, M Güttler, A Hartel, S Hartmann, ... Proceedings of the 2017 IEEE International Joint Conference on Neural Networks, 2017 | 11 | 2017 |
| Server side hashing core exceeding 3 Gbps of throughput HE Michail, GA Panagiotakopoulos, VN Thanasoulis, AP Kakarountas, ... International Journal of Security and Networks 2 (3-4), 228-238, 2007 | 9 | 2007 |
| Efficient Pipelined Hardware Implementation of RIPEMD-160 Hash Function HE Michail, VN Thanasoulis, GA Panagiotakopoulos, AP Kakarountas, ... International Journal of Electronics, Circuits and Systems 2 (2), 2008 | 7 | 2008 |
| A pulse communication flow ready for accelerated neuromorphic experiments V Thanasoulis, B Vogginger, J Partzsch, R Schüffny 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 265-268, 2014 | 4 | 2014 |
| Temporal and system level modifications for high speed VLSI implementations of cryptographic core HE Michail, AP Kakarountas, AS Milidonis, GA Panagiotakopoulos, ... 2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006 | 4 | 2006 |
| Analysis and Development of a Communication Infrastructure for a Wafer-Scale Neuromorphic System V Thanasoulis TUDpress, 2019 | 2 | 2019 |
| Configurable pulse routing architecture for accelerated multi-node neuromorphic systems V Thanasoulis, J Partzsch, B Vogginger, R Schüffny 2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014 | 2 | 2014 |
| Long-term pulse stimulation and recording in an accelerated neuromorphic system V Thanasoulis, J Partzsch, B Vogginger, C Mayr, R Schüffny 2012 19th IEEE International Conference on Electronics, Circuits, and …, 2012 | 2 | 2012 |
| Application Of Novel Techniques In RIPEMD-160 Hash Function Aiming At High-Throughput H Michail, V Thanasoulis, D Schinianakis, G Panagiotakopoulos, C Goutis HIGH PERFORMANCE COMPUTING & SIMULATION (HPCS 2008), 344, 2008 | 1 | 2008 |
| Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA V Thanasoulis, B Vogginger, J Partzsch, C Mayr 2021 28th IEEE International Conference on Electronics, Circuits, and …, 2021 | | 2021 |
| Server side hashing core exceeding 3 Gbps of throughput AP Kakarountas, VN Thanasoulis, HE Michail, GA Panagiotakopoulos, ... Inderscience Enterprises Ltd, 2007 | | 2007 |
| Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core AS Milidonis, AP Kakarountas, HE Michail, GA Panagiotakopoulos, ... | | 2006 |
