| Fault diagnosis and logic debugging using Boolean satisfiability A Smith, A Veneris, MF Ali, A Viglas IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 343 | 2005 |
| Astraea: A decentralized blockchain oracle J Adler, R Berryhill, A Veneris, Z Poulos, N Veira, A Kastania 2018 IEEE international conference on internet of things (IThings) and IEEE …, 2018 | 261 | 2018 |
| Improved design debugging using maximum satisfiability S Safarpour, H Mangassarian, A Veneris, MH Liffiton, KA Sakallah Formal Methods in Computer Aided Design (FMCAD'07), 13-19, 2007 | 157 | 2007 |
| Design error diagnosis and correction via test vector simulation A Veneris, IN Hajj IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999 | 134 | 1999 |
| Automated design debugging with maximum satisfiability Y Chen, S Safarpour, J Marques-Silva, A Veneris IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 117 | 2010 |
| Post-verification debugging of hierarchical designs MF Ali, S Safarpour, A Veneris, MS Abadir, R Drechsler ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 106 | 2005 |
| Design diagnosis using Boolean satisfiability A Smith, A Veneris, A Viglas ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004 | 93 | 2004 |
| Debugging sequential circuits using Boolean satisfiability MF Ali, A Veneris, S Safarpour, M Abadir, R Drechsler, A Smith Fifth International Workshop on Microprocessor Test and Verification (MTV'04 …, 2004 | 82 | 2004 |
| Incremental fault diagnosis JB Liu, A Veneris IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 79 | 2005 |
| Fault equivalence and diagnostic test generation using ATPG A Veneris, R Chang, MS Abadir, M Amiri 2004 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2004 | 77 | 2004 |
| Efficient SAT-based Boolean matching for FPGA technology mapping S Safarpour, A Veneris, G Baeckler, R Yuan Proceedings of the 43rd Annual Design Automation Conference, 466-471, 2006 | 61 | 2006 |
| A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test H Mangassarian, A Veneris, S Safarpour, M Benedetti, D Smith 2007 IEEE/ACM International Conference on Computer-Aided Design, 240-245, 2007 | 60 | 2007 |
| Privacy and transparency in cbdcs: A regulation-by-design aml/cft scheme N Pocher, A Veneris IEEE Transactions on Network and Service Management 19 (2), 1776-1788, 2021 | 58 | 2021 |
| Seamless integration of SER in rewiring-based design space exploration S Almukhaizim, Y Makris, YS Yang, A Veneris 2006 IEEE International Test Conference, 1-9, 2006 | 54 | 2006 |
| A truth-inducing sybil resistant decentralized blockchain oracle Y Cai, G Fragkos, EE Tsiropoulou, A Veneris 2020 2nd Conference on Blockchain Research & Applications for Innovative …, 2020 | 50 | 2020 |
| L-CBF: a low-power, fast counting Bloom filter architecture E Safi, A Moshovos, A Veneris Proceedings of the 2006 international symposium on Low power electronics and …, 2006 | 50 | 2006 |
| Abstraction and refinement techniques in automated design debugging S Safarpour, A Veneris 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 49 | 2007 |
| Robust QBF encodings for sequential circuits with applications to verification, debug, and test H Mangassarian, A Veneris, M Benedetti IEEE Transactions on Computers 59 (7), 981-994, 2010 | 45 | 2010 |
| On public crowdsource-based mechanisms for a decentralized blockchain oracle K Nelaturu, J Adler, M Merlini, R Berryhill, N Veira, Z Poulos, A Veneris IEEE Transactions on Engineering Management 67 (4), 1444-1458, 2020 | 42 | 2020 |
| Automating logic rectification by approximate SPFDs YS Yang, S Sinha, A Veneris, RK Brayton 2007 Asia and South Pacific Design Automation Conference, 402-407, 2007 | 42 | 2007 |
