| Gate array architecture using elevated metal levels for customization TR Gheewala, DG Breid, DD Sherlekar, MJ Colwell US Patent 6,617,621, 2003 | 195 | 2003 |
| N-channel and p-channel finFET cell architecture J Kawa, V Moroz, D Sherlekar US Patent 8,595,661, 2013 | 103 | 2013 |
| N-channel and P-channel finFET cell architecture with inter-block insulator J Kawa, V Moroz, D Sherlekar US Patent 8,561,003, 2013 | 75 | 2013 |
| Apparatuses and methods for efficient power rail structures for cell libraries D Sherlekar, D Heinecke, E Veluri US Patent 7,989,849, 2011 | 68 | 2011 |
| N-channel and p-channel end-to-end finfet cell architecture with relaxed gate pitch V Moroz, DD Sherlekar US Patent 8,723,268, 2014 | 65 | 2014 |
| Pin routing in standard cells DD Sherlekar, V Hovsepyan US Patent 8,612,914, 2013 | 55 | 2013 |
| Power routing in standard cell designs DD Sherlekar US Patent 8,513,978, 2013 | 55 | 2013 |
| Design considerations for regular fabrics DD Sherlekar Proceedings of the 2004 international symposium on Physical design, 97-102, 2004 | 39 | 2004 |
| Design planning for high-performance ASICs JY Sayah, R Gupta, DD Sherlekar, PS Honsinger, JM Apte, SW Bollinger, ... IBM Journal of Research and Development 40 (4), 431-452, 1996 | 38 | 1996 |
| FinFET cell architecture with power traces J Kawa, V Moroz, DD Sherlekar US Patent 8,924,908, 2014 | 30 | 2014 |
| Power routing in standard cells DD Sherlekar, V Hovsepyan US Patent 8,742,464, 2014 | 30 | 2014 |
| Various methods and apparatuses to preserve a logic state for a volatile latch circuit GT Sluss, DD Sherlekar, TR Gheewala US Patent 7,069,522, 2006 | 29 | 2006 |
| Cell architecture for increasing transistor size DD Sherlekar US Patent 8,631,374, 2014 | 26 | 2014 |
| 2nm node: Benchmarking FinFET vs nano-slab transistor architectures for artificial intelligence and next gen smart mobile devices SC Song, B Colombeau, M Bauer, V Moroz, XW Lin, P Asenov, ... 2019 Symposium on VLSI Technology, T206-T207, 2019 | 25 | 2019 |
| DTCO launches Moore’s law over the feature scaling wall V Moroz, XW Lin, P Asenov, D Sherlekar, M Choi, L Sponton, LS Melvin, ... 2020 IEEE International Electron Devices Meeting (IEDM), 41.1. 1-41.1. 4, 2020 | 20 | 2020 |
| FinFET cell architecture with insulator structure J Kawa, V Moroz, DD Sherlekar US Patent 9,048,121, 2015 | 19 | 2015 |
| Various methods and apparatuses to route multiple power rails to a cell DD Sherlekar, G Sluss, T Gheewala US Patent 7,219,324, 2007 | 19 | 2007 |
| Method and system for removing hardware design overlap DD Sherlekar, CR Selinger US Patent 5,943,243, 1999 | 17 | 1999 |
| Various methods and apparatuses to route multiple power rails to a cell DD Sherlekar, G Sluss, T Gheewala US Patent 8,132,142, 2012 | 16 | 2012 |
| FinFET cell architecture with power traces J Kawa, V Moroz, DD Sherlekar US Patent 9,691,764, 2017 | 14 | 2017 |
IV RamakrishnanProfessor of Computer Science, Assoc. Dean of Research, College of Engr. & Applied Sciences在 cs.stonybrook.edu 的电子邮件经过验证
