| High-Performance and Robust SRAM Cell Based on Asymmetric Dual-k Spacer FinFETs PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 60 (10), 3371 - 3377, 2013 | 77 | 2013 |
| Investigation of Symmetric Dual-(k) Spacer Trigate FinFETs From Delay Perspective PK Pal, BK Kaushik, S Dasgupta IEEE transactions on electron devices 61 (11), 2014 | 76 | 2014 |
| Asymmetric dual-spacer trigate FinFET device-circuit codesign and its variability analysis PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 62 (4), 1105-1112, 2015 | 59 | 2015 |
| New low-power techniques: Leakage feedback with Stack & Sleep stack with keeper PK Pal, RS Rathore, AK Rana, G Saini 2010 International Conference on Computer and Communication Technology …, 2010 | 33 | 2010 |
| Comparative analysis of STT and SOT based MRAMs for last level caches R Saha, YP Pundir, PK Pal Journal of Magnetism and Magnetic Materials 551, 169161, 2022 | 25 | 2022 |
| Design Metrics Improvement for SRAMs Using Symmetric Dual-k Spacer (SymD-k) FinFETs PK Pal, BK Kaushik, S Dasgupta IEEE Transactions on Electron Devices 61 (4), 1123-1130, 2014 | 25 | 2014 |
| Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits YP Pundir, R Saha, PK Pal Semiconductor Science and Technology 36 (1), 015010, 2020 | 17 | 2020 |
| Leakage behavior of underlap FinFET structure: A simulation study G Saini, AK Rana, PK Pal, S Jadav Computer and Communication Technology (ICCCT), 2010 International Conference …, 2010 | 16 | 2010 |
| Novel Feature Extraction Algorithm using DWT and Temporal Statistical Techniques for Word Dependent Speaker’s Recognition RK Singh, R Saha, PK Pal, G Singh 2018 Fourth International Conference on Research in Computational …, 2018 | 10 | 2018 |
| Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications RSPKP Yogendra Pratap Pundir, Arvind Bisht Silicon, 2022 | 9 | 2022 |
| Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor YP Pundir, A Bisht, R Saha, PK Pal Semiconductor Science and Technology 36 (9), 095037, 2021 | 9 | 2021 |
| Design of an area and energy-efficient last-level cache memory using STT-MRAM R Saha, YP Pundir, PK Pal Journal of Magnetism and Magnetic Materials 529, 167882, 2021 | 9 | 2021 |
| Spacer engineered FinFET architectures: high-performance digital circuit applications S Dasgupta, BK Kaushik, PK Pal CRC Press, 2017 | 9 | 2017 |
| High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications D Nehra, PK Pal, BK Kaushik, S Dasgupta 18th International Symposium on VLSI Design and Test, 1-6, 2014 | 9 | 2014 |
| Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers PK Pal, BK Kaushik, S Dasgupta VLSI Design and Test: 17th International Symposium, VDAT 2013, Jaipur, India …, 2013 | 8 | 2013 |
| Performance Enhancement of STT MRAM Using Asymmetric-Sidewall-Spacer NMOS S Verma, PK Pal, S Mahawar, BK Kaushik IEEE Transactions on Electron Devices 63 (7), 2771-2776, 2016 | 7 | 2016 |
| Analysis of Nanosheet Field Effect Transistor (NSFET) for device and circuit perspective P Kumar, S Yadav, PK Pal 2019 Women Institute of Technology Conference on Electrical and Computer …, 2019 | 6 | 2019 |
| Enhanced device performance using lightly doped channel junctionless accumulation-mode FinFET PK Pal, D Nehra, BK Kaushik, S Dasgupta 2015 12th International Conference on Electrical Engineering/Electronics …, 2015 | 6 | 2015 |
| Performance analysis of dual-k spacer at source side for underlap FinFETs PK Pal, P Singh, BK Kaushik, B Anand, S Dasgupta India Conference (INDICON), 2012 Annual IEEE, 915-919, 2012 | 6 | 2012 |
| Attention based hybrid deep learning model for wearable based stress recognition R Tanwar, OC Phukan, G Singh, PK Pal, S Tiwari Engineering Applications of Artificial Intelligence 127, 107391, 2024 | 5 | 2024 |
Brajesh Kumar KaushikProfessor of Electronics and Communication Engg., IIT-Roorkee在 iitr.ac.in 的电子邮件经过验证
