| 16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced … J Kim, H Yoon, Y Lim, Y Lee, Y Cho, T Seong, J Choi 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 258-260, 2019 | 68 | 2019 |
| A low-integrated-phase-noise 27–30-GHz injection-locked frequency multiplier with an ultra-low-power frequency-tracking loop for mm-wave-band 5G transceivers S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi IEEE Journal of Solid-State Circuits 53 (2), 375-388, 2017 | 63 | 2017 |
| A− 31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection … H Yoon, J Kim, S Park, Y Lim, Y Lee, J Bang, K Lim, J Choi 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 366-368, 2018 | 54 | 2018 |
| A Wideband Dual-Mode -VCO With a Switchable Gate-Biased Active Core H Yoon, Y Lee, JJ Kim, J Choi IEEE Transactions on Circuits and Systems II: Express Briefs 61 (5), 289-293, 2014 | 46 | 2014 |
| A 0.56–2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G–4G Multistandard Cellular Transceivers H Yoon, Y Lee, Y Lim, GY Tak, HT Kim, YC Ho, J Choi IEEE Journal of Solid-State Circuits 51 (3), 614-625, 2016 | 40 | 2016 |
| An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators J Kim, Y Lim, H Yoon, Y Lee, H Park, Y Cho, T Seong, J Choi IEEE Journal of Solid-State Circuits 54 (12), 3466-3477, 2019 | 37 | 2019 |
| 19.2 A PVT-robust− 39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase … S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi 2017 IEEE International Solid-State Circuits Conference (ISSCC), 324-325, 2017 | 36 | 2017 |
| A PVT-robust −59-dBc reference spur and 450-fsRMSjitter injection-locked clock multiplier using a voltage-domain period-calibrating loop Y Lee, H Yoon, M Kim, J Choi 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 25 | 2016 |
| 17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power … Y Lim, J Kim, Y Jo, J Bang, S Yoo, H Park, H Yoon, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 280-282, 2020 | 21 | 2020 |
| 23.4 An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS S Yoo, S Park, S Choi, Y Cho, H Yoon, C Hwang, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 330-332, 2021 | 15 | 2021 |
| A low-jitter injection-locked multi-frequency generator using digitally controlled oscillators and time-interleaved calibration H Yoon, S Park, J Choi IEEE Journal of Solid-State Circuits 54 (6), 1564-1574, 2019 | 13 | 2019 |
| Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 303-304, 2018 | 1 | 2018 |
| An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration S Park, H Yoon, J Choi 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 329-332, 2017 | 1 | 2017 |
| An Ultra-Low Integrated-Phase-Noise 28-GHz LO Generator for 5G Transceivers Supporting Multiple Frequency Bands H Yoon, S Park, J Kim, J Choi 2022 IEEE International Symposium on Radio-Frequency Integration Technology …, 2022 | | 2022 |
| ISSCC 2017/SESSION 19/FREQUENCY GENERATION/19.2 S Yoo, S Choi, J Kim, H Yoon, Y Lee, J Choi | | |
Yongsun Lee (이용선)Memory division, Samsung Electronics在 samsung.com 的电子邮件经过验证
