| Energy-efficient abundant-data computing: The N3XT 1,000 x MMS Aly, M Gao, G Hills, CS Lee, G Pitner, MM Shulaker, TF Wu, ... Computer 48 (12), 24-33, 2015 | 282 | 2015 |
| Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs MM Shulaker, TF Wu, A Pal, L Zhao, Y Nishi, K Saraswat, HSP Wong, ... 2014 IEEE International Electron Devices Meeting, 27.4. 1-27.4. 4, 2014 | 187 | 2014 |
| Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study TF Wu, H Li, PC Huang, A Rahimi, JM Rabaey, HSP Wong, MM Shulaker, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 492-494, 2018 | 144 | 2018 |
| Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition H Li, TF Wu, A Rahimi, KS Li, M Rusch, CH Lin, JL Hsu, MM Sabry, ... 2016 IEEE International Electron Devices Meeting (IEDM), 16.1. 1-16.1. 4, 2016 | 142 | 2016 |
| The N3XT Approach to Energy-Efficient Abundant-Data Computing MMS Aly, TF Wu, A Bartolo, YH Malviya, W Hwang, G Hills, I Markov, ... Proceedings of the IEEE 107 (1), 19-48, 2018 | 129 | 2018 |
| TPAD: Hardware Trojan prevention and detection for trusted integrated circuits TF Wu, K Ganesan, YA Hu, HSP Wong, S Wong, S Mitra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 113 | 2015 |
| Carbon nanotube circuit integration up to sub-20 nm channel lengths MM Shulaker, J Van Rethy, TF Wu, L Suriyasena Liyanage, H Wei, Z Li, ... ACS nano 8 (4), 3434-3443, 2014 | 95 | 2014 |
| Monolithic 3D integration: A path from concept to reality MM Shulaker, TF Wu, MM Sabry, H Wei, HSP Wong, S Mitra 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 81 | 2015 |
| Hyperdimensional computing exploiting carbon nanotube FETs, resistive RAM, and their monolithic 3D integration TF Wu, H Li, PC Huang, A Rahimi, G Hills, B Hodson, W Hwang, ... IEEE Journal of Solid-State Circuits 53 (11), 3183-3196, 2018 | 75 | 2018 |
| Resistive RAM-centric computing: Design and modeling methodology H Li, TF Wu, S Mitra, HSP Wong IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2263-2273, 2017 | 73 | 2017 |
| Resistive RAM endurance: Array-level characterization and correction techniques targeting deep learning applications A Grossi, E Vianello, MM Sabry, M Barlas, L Grenouillet, J Coignus, ... IEEE Transactions on Electron Devices 66 (3), 1281-1288, 2019 | 66 | 2019 |
| Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell BQ Le, A Grossi, E Vianello, T Wu, G Lama, E Beigne, HSP Wong, S Mitra IEEE Transactions on Electron Devices 66 (1), 641-646, 2018 | 62 | 2018 |
| Cooling three-dimensional integrated circuits using power delivery networks H Wei, TF Wu, D Sekar, B Cronquist, RF Pease, S Mitra 2012 International Electron Devices Meeting, 14.2. 1-14.2. 4, 2012 | 52 | 2012 |
| High-density multiple bits-per-cell 1T4R RRAM array with gradual SET/RESET and its effectiveness for deep learning ER Hsieh, M Giordano, B Hodson, A Levy, SK Osekowsky, RM Radway, ... 2019 IEEE International Electron Devices Meeting (IEDM), 35.6. 1-35.6. 4, 2019 | 50 | 2019 |
| Efficient metallic carbon nanotube removal for highly-scaled technologies MM Shulaker, G Hills, TF Wu, Z Bao, HSP Wong, S Mitra 2015 IEEE International Electron Devices Meeting (IEDM), 32.4. 1-32.4. 4, 2015 | 45 | 2015 |
| RADAR: A fast and energy-efficient programming technique for multiple bits-per-cell RRAM arrays BQ Le, A Levy, TF Wu, RM Radway, ER Hsieh, X Zheng, M Nelson, ... IEEE Transactions on Electron Devices 68 (9), 4397-4403, 2021 | 35 | 2021 |
| Monolithic 3D integration advances and challenges: From technology to system levels MS Ebrahimi, G Hills, MM Sabry, MM Shulaker, H Wei, TF Wu, S Mitra, ... 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S …, 2014 | 28 | 2014 |
| System-level design and integration of a prototype AR/VR hardware featuring a custom low-power DNN accelerator chip in 7nm technology for codec avatars HE Sumbul, TF Wu, Y Li, SS Sarwar, W Koven, E Murphy-Trotzky, X Cai, ... 2022 IEEE Custom Integrated Circuits Conference (CICC), 01-08, 2022 | 26 | 2022 |
| 14.3 A 43pJ/cycle non-volatile microcontroller with 4.7 μs shutdown/wake-up integrating 2.3-bit/cell resistive RAM and resilience techniques TF Wu, BQ Le, R Radway, A Bartolo, W Hwang, S Jeong, H Li, P Tandon, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 226-228, 2019 | 22 | 2019 |
| 3D nanosystems enable embedded abundant-data computing: special session paper W Hwang, MMS Aly, YH Malviya, M Gao, TF Wu, C Kozyrakis, HSP Wong, ... Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on …, 2017 | 17* | 2017 |
H.-S. Philip WongProfessor of Electrical Engineering, Stanford University在 stanford.edu 的电子邮件经过验证
