Trace cache: a low latency approach to high bandwidth instruction fetching E Rotenberg, S Bennett, JE Smith Proceedings of the 29th Annual IEEE/ACM International Symposium on …, 1996 | 897 | 1996 |
AR-SMT: A microarchitectural approach to fault tolerance in microprocessors E Rotenberg Digest of Papers. Twenty-Ninth Annual International Symposium on Fault …, 1999 | 702 | 1999 |
Trace processors E Rotenberg, Q Jacobson, Y Sazeides, J Smith Proceedings of 30th Annual International Symposium on Microarchitecture, 138-148, 1997 | 533 | 1997 |
Slipstream processors: Improving both performance and fault tolerance K Sundaramoorthy, Z Purser, E Rotenberg ACM SIGPLAN Notices 35 (11), 257-268, 2000 | 463 | 2000 |
Assigning confidence to conditional branch predictions E Jacobsen, E Rotenberg, JE Smith Proceedings of the 29th Annual IEEE/ACM International Symposium on …, 1996 | 447 | 1996 |
A large, fast instruction window for tolerating cache misses AR Lebeck, J Koppanalil, T Li, J Patwardhan, E Rotenberg ACM SIGARCH Computer Architecture News 30 (2), 59-70, 2002 | 300 | 2002 |
Retention-aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM RK Venkatesan, S Herr, E Rotenberg The Twelfth International Symposium on High-Performance Computer …, 2006 | 265 | 2006 |
Path-based next trace prediction Q Jacobson, E Rotenberg, JE Smith Proceedings of 30th Annual International Symposium on Microarchitecture, 14-23, 1997 | 259 | 1997 |
Adaptive mode control: A static-power-efficient cache design H Zhou, MC Toburen, E Rotenberg, TM Conte ACM Transactions on Embedded Computing Systems (TECS) 2 (3), 347-372, 2003 | 253 | 2003 |
FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template NK Choudhary, SV Wadhavkar, TA Shah, H Mayukh, J Gandhi, BH Dwiel, ... ACM SIGARCH Computer Architecture News 39 (3), 11-22, 2011 | 195 | 2011 |
A trace cache microarchitecture and evaluation E Rotenberg, S Bennett, JE Smith IEEE Transactions on Computers 48 (2), 111-120, 1999 | 146 | 1999 |
Fast: Frequency-aware static timing analysis K Seth, A Anantaraman, F Mueller, E Rotenberg ACM Transactions on Embedded Computing Systems (TECS) 5 (1), 200-224, 2006 | 141 | 2006 |
A study of slipstream processors Z Purser, K Sundaramoorthy, E Rotenberg Proceedings of the 33rd annual ACM/IEEE International Symposium on …, 2000 | 138 | 2000 |
Systems, methods and devices for providing variable-latency write operations in memory devices E Rotenberg, RK Venkatesan, AS Al-Zawawi US Patent 7,099,215, 2006 | 119 | 2006 |
A study of control independence in superscalar processors E Rotenberg, Q Jacobson, J Smith Proceedings Fifth International Symposium on High-Performance Computer …, 1999 | 108 | 1999 |
Virtual simple architecture (VISA) exceeding the complexity limit in safe real-time systems A Anantaraman, K Seth, K Patil, E Rotenberg, F Mueller Proceedings of the 30th annual international symposium on Computer …, 2003 | 101 | 2003 |
Control independence in trace processors E Rotenberg, J Smith MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999 | 95 | 1999 |
A case for dynamic pipeline scaling J Koppanalil, P Ramrakhyani, S Desai, A Vaidyanathan, E Rotenberg Proceedings of the 2002 international conference on Compilers, architecture …, 2002 | 69 | 2002 |
Understanding prediction-based partial redundant threading for low-overhead, high-coverage fault tolerance VK Reddy, E Rotenberg, S Parthasarathy ACM SIGARCH Computer Architecture News 34 (5), 83-94, 2006 | 63 | 2006 |
Transparent control independence (TCI) AS Al-Zawawi, VK Reddy, E Rotenberg, HH Akkary ACM SIGARCH Computer Architecture News 35 (2), 448-459, 2007 | 53 | 2007 |