| Interconnects in the third dimension: Design challenges for 3D ICs K Bernstein, P Andry, J Cann, P Emma, D Greenberg, W Haensch, ... Proceedings of the 44th annual Design Automation Conference, 562-567, 2007 | 427 | 2007 |
| Merged logic and memory combining thin film and bulk Si transistors PG Emmma, W Hwang, SM Gates US Patent 6,620,659, 2003 | 357 | 2003 |
| Clock skew minimization system and method for integrated circuits FM Bozso, PG Emma US Patent 5,760,478, 1998 | 257 | 1998 |
| 3-dimensional integrated circuit architecture, structure and method for fabrication thereof K Bernstein, PW Coteus, PG Emma US Patent 7,408,798, 2008 | 255 | 2008 |
| Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof K Bernstein, PW Coteus, PG Emma US Patent 7,684,224, 2010 | 243 | 2010 |
| Branch history table prediction of moving target branches due to subroutine returns DR Kaeli, PG Emma ACM SIGARCH Computer Architecture News 19 (3), 34-42, 1991 | 242 | 1991 |
| 3-dimensional integrated circuit architecture, structure and method for fabrication thereof K Bernstein, PW Coteus, PG Emma US Patent 7,692,944, 2010 | 231 | 2010 |
| Is 3D chip technology the next growth engine for performance improvement? PG Emma, E Kursun IBM journal of research and development 52 (6), 541-552, 2008 | 190 | 2008 |
| Optimizing pipelines for power and performance V Srinivasan, D Brooks, M Gschwind, P Bose, V Zyuban, PN Strenski, ... 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002 | 183 | 2002 |
| Three-dimensional architecture for self-checking and self-repairing integrated circuits K Bernstein, PW Coteus, IAM Elfadel, PG Emma, KW Guarini, ... US Patent App. 11/621,188, 2008 | 182 | 2008 |
| New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors D Brooks, P Bose, V Srinivasan, MK Gschwind, PG Emma, MG Rosenfield IBM Journal of Research and Development 47 (5.6), 653-670, 2003 | 162 | 2003 |
| Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture PG Emma US Patent 5,619,665, 1997 | 119 | 1997 |
| Understanding some simple processor-performance limits PG Emma IBM journal of Research and Development 41 (3), 215-232, 1997 | 115 | 1997 |
| Dynamic memory architecture employing passive expiration of data PG Emma, RK Montoye, WR Reohr US Patent 7,290,203, 2007 | 111 | 2007 |
| Method and apparatus for prefetching branch history information PG Emma, KJ Getzlaff, AM Hartstein, T Pflueger, TR Puzak, EM Schwarz, ... US Patent 7,493,480, 2009 | 109 | 2009 |
| Dynamic memory architecture employing passive expiration of data PG Emma, RK Montoye, WR Reohr US Patent 8,020,073, 2011 | 108 | 2011 |
| Recovery unit for mirrored processors FM Bozso, YH Chan, PG Emma, AJ Gruodis, DP Hillerud, SB Swaney US Patent 5,692,121, 1997 | 104 | 1997 |
| Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions PG Emma, JH Pomerene, RN Rechtschaffen, FJ Sparacio US Patent 4,991,080, 1991 | 103 | 1991 |
| Simultaneous prediction of multiple branches for superscalar processing PG Emma, JW Knight, JH Pomerene, TR Puzak US Patent 5,434,985, 1995 | 102 | 1995 |
| A 400-MHz s/390 microprocessor CF Webb, CJ Anderson, L Sigal, KL Shepard, JS Liptay, JD Warnock, ... IEEE Journal of Solid-State Circuits 32 (11), 1665-1675, 1997 | 97 | 1997 |
