| ALL digital phase-locked loop (ADPLL): a survey K Lata, M Kumar International Journal of Future Computer and Communication 2 (6), 551, 2013 | 27 | 2013 |
| Design and implementation of combined pipelining and parallel processing architecture for FIR and IIR filters using VHDL J Potsangbam, M Kumar International Journal of VLSI Design and Communication Systems 10 (4), 1-16, 2019 | 14 | 2019 |
| FPGA implementation of ADPLL with Ripple Reduction Techniques M Kumar, K Lata International Journal of VLSI design & Communication Systems (VLSICS) 3 (2 …, 2012 | 14 | 2012 |
| Design and Implementation of FPGA based Vending Machine for Integrated Circuit (IC) E Kho, M Kumar 2020 International Conference on Communication and Signal Processing (ICCSP …, 2020 | 12 | 2020 |
| Design and Implementation of an improved carry increment adder AB Devi, M Kumar, R Laishram arXiv preprint arXiv:1603.04094, 2016 | 12 | 2016 |
| ADPLL Design and Implementation on FPGA K Lata, M Kumar 2013 International Conference on Intelligent Systems and Signal Processing …, 2013 | 12 | 2013 |
| Content based medical image retrieval system (CBMIRS) to diagnose hepatobiliary images M Kumar, KM Singh Smart and Innovative Trends in Next Generation Computing Technologies: Third …, 2018 | 10 | 2018 |
| FPGA implementation of true random number generator architecture using all digital phase-locked loop H Bharat Meitei, M Kumar IETE Journal of Research 68 (3), 1561-1570, 2022 | 9 | 2022 |
| Retrieval of head–neck medical images using Gabor filter based on power-law transformation method and rank BHMT M Kumar, KM Singh Signal, Image and Video Processing 12 (5), 827-833, 2018 | 9 | 2018 |
| Design and implementation of ADPLL for digital communication applications AK Chaudhary, M Kumar 2017 2nd International Conference for Convergence in Technology (I2CT), 397-401, 2017 | 7 | 2017 |
| All digital phase locked loop (ADPLL): a survey M Kumar, K Lata Proceeding the 4th IEEE international conference on electronics computer …, 2012 | 7 | 2012 |
| Design and implementation of higher order sigma delta modulator circuits using FPAA DD Roel, M Kumar Analog Integrated Circuits and Signal Processing 104 (2), 169-182, 2020 | 6 | 2020 |
| Vlsi Implementation of Area Efficient 2-Parallel Fir Digital Filter LK Phimu, M Kumar International Journal of VLSI design & Communication Systems (VLSICS) Vol 7, 2016 | 4 | 2016 |
| Content based medical image retrieval system using DWT and LBP for ear images M Kumar, KM Singh JCTA 9 (40), 353-358, 2016 | 4 | 2016 |
| Vhdl implementation of noc architecture for uart using round robin arbiter B Khataniar, M Kumar Computational Intelligence, Communications, and Business Analytics: First …, 2017 | 3 | 2017 |
| Design of IIR systolic array architecture by using linear mapping technique M Kumar International Journal of Computer Applications 182 (39), 14-19, 2019 | 1 | 2019 |
| Retrieval of X-ray images using scale invariant feature transform and combination of region and elliptic Fourier descriptors feature M Kumar, KM Singh Journal of Medical Imaging and Health Informatics 8 (4), 755-760, 2018 | 1 | 2018 |
| Design and implementation of area efficient 2-parallel filter on FPGA using image system LK Phimu, M Kumar 2017 International Conference on Innovative Research In Electrical Sciences …, 2017 | 1 | 2017 |
| Content based medical image retrieval system using fourier descriptors feature for nose images M Kumar, KM Singh SSRG International Journal of Electronics and Communication Engineering …, 2016 | 1 | 2016 |
| Implementation of Word Level Parallel Processing Unfolding Algorithm using VHDL M Kumar, K Ram | 1 | |
