| The impact of resource partitioning on SMT processors SE Raasch, SK Reinhardt 2003 12th International Conference on Parallel Architectures and Compilation …, 2003 | 183 | 2003 |
| A scalable instruction queue design using dependence chains SE Raasch, NL Binkert, SK Reinhardt ACM SIGARCH Computer Architecture News 30 (2), 318-329, 2002 | 137 | 2002 |
| Design and Analysis of an APU for Exascale Computing T Vijayaraghavan, Y Eckert, GH Loh, MJ Schulte, M Ignatowski, ... 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 98 | 2017 |
| Applications of thread prioritization in SMT processors SE Raasch, SK Reinhardt Proc. of the Workshop on Multithreaded Execution And Compilation, 1999 | 57 | 1999 |
| Integrating superscalar processor components to implement register caching M Postiff, D Greene, S Raasch, T Mudge Proceedings of the 15th international conference on Supercomputing, 348-357, 2001 | 51 | 2001 |
| Compiler techniques to reduce the synchronization overhead of gpu redundant multithreading M Gupta, D Lowell, J Kalamatianos, S Raasch, V Sridharan, D Tullsen, ... Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 37 | 2017 |
| On characterizing near-threshold SRAM failures in FinFET technology S Ganapathy, J Kalamatianos, K Kasprak, S Raasch Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 36 | 2017 |
| Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system PB Racunas, JS Emer, A Biswas, SS Mukherjee, SE Raasch US Patent 7,747,932, 2010 | 30 | 2010 |
| Selective activation of error mitigation based on bit level error count A Biswas, S Raasch, S Mukherjee US Patent App. 11/151,818, 2007 | 29 | 2007 |
| Lifetime memory reliability data from the field T Siddiqua, V Sridharan, SE Raasch, N DeBardeleben, KB Ferreira, ... 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2017 | 26 | 2017 |
| A fast and accurate analytical technique to compute the AVF of sequential bits in a processor S Raasch, A Biswas, J Stephan, P Racunas, J Emer Proceedings of the 48th International Symposium on Microarchitecture, 738-749, 2015 | 26 | 2015 |
| Improving dram fault characterization through machine learning E Baseman, N DeBardeleben, K Ferreira, S Levy, S Raasch, V Sridharan, ... 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016 | 19 | 2016 |
| Prioritizing local and remote memory access in a non-uniform memory access architecture MW Boyer, O Kayiran, Y Eckert, S Raasch, MSBIN ALTAF US Patent 10,838,864, 2020 | 18 | 2020 |
| Obtaining data for redundant multithreading (RMT) execution GJ Hinton, SE Raasch, S Hily, JG Holm, R Singhal, A Sodani, DT Marr, ... US Patent 9,081,688, 2015 | 17 | 2015 |
| General purpose hardware to replace faulty core components that may also provide additional processor functionality SE Raasch, MD Powell, SS Mukherjee, A Biswas US Patent 8,914,672, 2014 | 14 | 2014 |
| State history storage for synchronizing redundant processors SS Mukherjee, A Biswas, PB Racunas, SE Raasch US Patent 8,171,328, 2012 | 14 | 2012 |
| Killi: Runtime fault classification to deploy low voltage caches without MBIST S Ganapathy, J Kalamatianos, BM Beckmann, S Raasch, LG Szafaryn 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 12 | 2019 |
| Localizing error detection and recovery A Biswas, S Raasch, S Mukherjee, S Mitra US Patent App. 11/026,220, 2006 | 10 | 2006 |
| Method and apparatus for mitigating row hammer attacks S Seyedzadehdelcheh, S Raasch US Patent 10,950,292, 2021 | 8 | 2021 |
| Performance-aware and reliability-aware data placement for n-level heterogeneous memory systems M Gupta, DA Roberts, MR Meswani, V Sridharan, S Raasch, DI Lowell US Patent 10,365,996, 2019 | 7 | 2019 |
Steven K. ReinhardtMicrosoft在 microsoft.com 的电子邮件经过验证
