| WinoNN: Optimizing FPGA-based convolutional neural network accelerators using sparse Winograd algorithm X Wang, C Wang, J Cao, L Gong, X Zhou IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 41 | 2020 |
| Work-in-progress: WinoNN: Optimising FPGA-based neural network accelerators using fast winograd algorithm X Wang, C Wang, X Zhou 2018 International Conference on Hardware/Software Codesign and System …, 2018 | 9 | 2018 |
| UH-JLS: A parallel ultra-high throughput JPEG-LS encoding architecture for lossless image compression X Wang, L Gong, C Wang, X Li, X Zhou 2021 IEEE 39th International Conference on Computer Design (ICCD), 335-343, 2021 | 4 | 2021 |
| HAP: A spatial-von neumann heterogeneous automata processor with optimized resource and IO overhead on FPGA X Wang, L Gong, J Cao, W Lou, W Wang, C Wang, X Zhou Proceedings of the 2023 ACM/SIGDA International Symposium on Field …, 2023 | 3 | 2023 |
| NAF: Deeper Network/Accelerator Co-Exploration for Customizing CNNs on FPGA W Lou, J Qian, L Gong, X Wang, C Wang, X Zhou 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 2 | 2023 |
