| A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS D Linten, S Thijs, MI Natarajan, P Wambacq, W Jeamsaksiri, J Ramos, ... IEEE Journal of Solid-State Circuits 40 (7), 1434-1442, 2005 | 189 | 2005 |
| Exhaust aftertreatment device, including chemical mixing and acoustic effects ZG Liu, MT Zuroski, CD Bremigan, KJ Kicinski, CR Cheng US Patent 6,722,123, 2004 | 141 | 2004 |
| Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage V De Heyn, G Groeseneken, B Keppens, M Natarajan, L Vacaresse, ... 2001 IEEE International Reliability Physics Symposium Proceedings. 39th …, 2001 | 65 | 2001 |
| T-diodes-a novel plug-and-play wideband RF circuit ESD protection methodology D Linten, S Thijs, J Borremans, M Dehan, D Tremouilles, M Scholz, ... 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD …, 2007 | 52 | 2007 |
| Calibrated wafer-level HBM measurements for quasi-static and transient device analysis M Scholz, S Thijs, D Linten, D Tremouilles, M Sawada, T Nakaei, ... 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD …, 2007 | 50 | 2007 |
| Electrostatic discharge protected circuits S Thijs, NM Iyer, D Linten US Patent 7,649,722, 2010 | 45 | 2010 |
| Standardization of the transmission line pulse (TLP) methodology for electrostatic discharge (ESD) SH Voldman, R Ashton, J Barth, D Bennett, J Bernier, M Chaine, ... 2003 Electrical Overstress/Electrostatic Discharge Symposium, 1-10, 2003 | 38 | 2003 |
| Transient voltage overshoot in TLP testing–Real or artifact? D Trémouilles, S Thijs, P Roussel, MI Natarajan, V Vassilev, ... Microelectronics Reliability 47 (7), 1016-1024, 2007 | 34 | 2007 |
| A 6.5-kV ESD-protected 3-5-GHz ultra-wideband BiCMOS low-noise amplifier using interstage gain roll-off compensation M Liu, J Craninckx, NM Iyer, M Kuijk, ARF Barel IEEE transactions on microwave theory and techniques 54 (4), 1698-1706, 2006 | 33 | 2006 |
| Contributions to standardization of transmission line pulse testing methodology B Keppens, V De Heyn, MN Iyer, G Groeseneken 2001 Electrical Overstress/Electrostatic Discharge Symposium, 456-462, 2001 | 26 | 2001 |
| A low-cost 90nm RF-CMOS platform for record RF circuit performance W Jeamsaksiri, D Linten, S Thijs, G Carchon, J Ramos, A Mercha, X Sun, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 60-61, 2005 | 25 | 2005 |
| Surface oxidation of nickel thin films SV Kumari, M Natarajan, VK Vaidyan, P Koshy Journal of materials science letters 11, 761-762, 1992 | 24 | 1992 |
| Three-dimensional electrostatic discharge semiconductor device J Singh, A Wei, MI Natarajan US Patent 9,177,951, 2015 | 20 | 2015 |
| Turn-off characteristics of the CMOS snapback ESD protection devices-new insights and its implications VA Vashchenko, M Scholz, P Jansen, R Petersen, MI Natarajan, ... 2006 Electrical Overstress/Electrostatic Discharge Symposium, 39-45, 2006 | 20 | 2006 |
| RFCMOS ESD protection and reliability MI Natarajan, S Thijs, P Jansen, D Tremouilles, W Jeamsaksiri, ... Proceedings of the 12th International Symposium on the Physical and Failure …, 2005 | 20 | 2005 |
| Test circuits for fast and reliable assessment of CDM robustness of I/O stages W Stadler, K Esmark, K Reynders, M Zubeidat, M Graf, W Wilkening, ... Microelectronics Reliability 45 (2), 269-277, 2005 | 20 | 2005 |
| ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS—Implementation concepts, constraints and solutions S Thijs, MI Natarajan, D Linten, V Vassilev, T Daenen, A Scholten, ... 2004 Electrical Overstress/Electrostatic Discharge Symposium, 1-10, 2004 | 20 | 2004 |
| Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors D Linten, X Sun, S Thijs, MI Natarajan, A Mercha, G Carchon, P Wambacq, ... Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 …, 2005 | 18 | 2005 |
| An integrated 5 GHz low-noise amplifier with 5.5 kV HBM ESD protection in 90 nm RF CMOS D Linten, S Thijs, W Jeamsaksiri, J Ramos, A Mercha, MI Natarajan, ... Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005., 86-89, 2005 | 18 | 2005 |
| Novel stress-free keep out zone process development for via middle TSV in 20nm planar CMOS technology MA Rabie, CS Premachandran, R Ranjan, MI Natarajan, SF Yap, D Smith, ... IEEE International Interconnect Technology Conference, 203-206, 2014 | 17 | 2014 |
Guido Groesenekenimec and KU Leuven在 imec.be 的电子邮件经过验证
