| The gem5 Simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 256 | 2020 |
| Simulating Multi-Core RISC-V Systems in gem5 T Ta, L Cheng, C Batten Workshop on Computer Architecture Research with RISC-V, 2018 | 32 | 2018 |
| The gem5 Simulator: Version 20.0+. CoRR abs/2007.03152 (2020) J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 12 | 2020 |
| Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems M Wang, T Ta, L Cheng, C Batten 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 10 | 2020 |
| Autonomous Data-Race-Free GPU Testing T Ta, X Zhang, A Gutierrez, BM Beckmann 2019 IEEE International Symposium on Workload Characterization (IISWC), 81-92, 2019 | 8 | 2019 |
| Accelerating DynEarthSol3D on tightly coupled CPU–GPU heterogeneous processors T Ta, K Choo, E Tan, B Jang, E Choi Computers & geosciences 79, 27-37, 2015 | 8 | 2015 |
| A Specialized Concurrent Queue for Scheduling Irregular Workloads on GPUs D Troendle, T Ta, B Jang Proceedings of the 48th International Conference on Parallel Processing, 51, 2019 | 6 | 2019 |
| AMD gem5 APU simulator: Modeling GPU s Using the Machine ISA A Gutierrez, S Puthoor, B Beckmann, T Ta Tutorial at International Symposium on Computer Architecture, 2018 | 6 | 2018 |
| Power delivery and thermal-aware arm-based multi-tier 3D architecture L Zhu, T Ta, R Liu, R Mathur, X Xu, S Das, A Kaul, A Rico, D Joseph, ... 2021 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2021 | 5 | 2021 |
| Understanding the Impact of Fine-Grained Data Sharing and Thread Communication on Heterogeneous Workload Development T Ta, D Troendle, X Hu, B Jang 2017 16th International Symposium on Parallel and Distributed Computing …, 2017 | 5 | 2017 |
| A New Era of Silicon Prototyping in Computer Architecture Research C Torng, S Jiang, K Al-Hawaj, I Bukreyev, B Ilbeyi, T Ta, L Cheng, ... The RISC-V Day Workshop at the 51st Int’l Symp. on Microarchitecture, 2018 | 4 | 2018 |
| Implementation of a scalable, performance portable shallow water equation solver using radial basis function-generated finite difference methods S Elliott, RRP Kumar, N Flyer, T Ta, R Loft The International Journal of High Performance Computing Applications …, 2018 | 4 | 2018 |
| CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA TJ Chang, A Li, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 3 | 2023 |
| big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip T Ta, K Al-Hawaj, N Cebry, Y Ou, E Hall, C Golden, C Batten | 3* | |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 2 | 2023 |
| Thread communication and synchronization on massively parallel GPUs T Ta, D Troendle, B Jang Advances in GPU Research and Practice, 57-81, 2017 | 2 | 2017 |
| EVE: Ephemeral Vector Engines K Al-Hawaj, T Ta, N Cebry, S Agwa, O Afuye, E Hall, C Golden, AB Apsel, ... 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 1 | 2023 |
| Vectorized Operations for Sparse Kernels J Randall, JG Beu, K Nathella, TQ Ta US Patent US 20230367843A1, 2023 | | 2023 |
| The gem5 Simulator: Version 20.0+: A new era for the open-source computer architecture simulator J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... ArXivorg, 2020 | | 2020 |
| The Case for Using Guix to Enable Reproducible RISC-V So ware & Hardware C Batten, P Prins, E Flashner, A Isaac, J Nieuwenhuizen, E Zarraga, T Ta, ... | | |
