| Neutron-and proton-induced single event upsets for D-and DICE-flip/flop designs at a 40 nm technology node TD Loveless, S Jagannathan, T Reece, J Chetia, BL Bhuva, MW McCurdy, ... IEEE Transactions on Nuclear Science 58 (3), 1008-1014, 2011 | 175 | 2011 |
| Independent measurement of SET pulse widths from N-hits and P-hits in 65-nm CMOS S Jagannathan, MJ Gadlage, BL Bhuva, RD Schrimpf, B Narasimham, ... IEEE Transactions on Nuclear Science 57 (6), 3386-3391, 2010 | 71 | 2010 |
| Redefine: Runtime reconfigurable polymorphic asic M Alle, K Varadarajan, A Fell, N Joseph, S Das, P Biswas, J Chetia, A Rao, ... ACM Transactions on Embedded Computing Systems (TECS) 9 (2), 1-48, 2009 | 65 | 2009 |
| Generic routing rules and a scalable access enhancement for the network-on-chip reconnect A Fell, P Biswas, J Chetia, SK Nandy, R Narayan 2009 IEEE International SOC Conference (SOCC), 251-254, 2009 | 18 | 2009 |
| Streaming FFT on REDEFINE-v2: An application-architecture design space exploration A Fell, M Alle, K Varadarajan, P Biswas, S Das, J Chetia, SK Nandy, ... Proceedings of the 2009 international conference on Compilers, architecture …, 2009 | 13 | 2009 |
| An efficient AVF estimation technique using circuit partitioning J Chetia, BD Sierawski, AL Sternberg, AA Adeleke, BL Bhuva, ... 2011 12th European Conference on Radiation and Its Effects on Components and …, 2011 | 2 | 2011 |
| IEEE Trans. Nucl. Sci. S Jagannatha, MJ Gadlage, BL Bhuva, RD Schrimpf, B Narasimham, ... IEEE Trans. Nucl. Sci, 2006 | 2 | 2006 |
| Efficient Pipeline Stage Generator for Shift Left Large ASIC Design Planning EH See, J Chetia Intel's Internal Technical Conference 2022, 2022 | | 2022 |
| High Speed SerDes Subsystem Physical Implementation for a 5G ASIC J Chetia, WC Lim Intel's Internal Technical Conference 2021, 2021 | | 2021 |
| Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture B Suparjo, J Chetia, AR Shah IEEE International Test Conference 2021, pp. 339-343, 2021 | | 2021 |
| Design Planning Solutions on an Advanced Process Test Chip J Chetia, NK Subramanya, P Thakyal, L Kong, P Welling Intel's Internal Technical Conference 2020, 2020 | | 2020 |
| A Case Study of Flexible Clock Distribution Methodology for Complex SoC EK Teh, WC Lim, J Chetia, P Welling, R Perez Intel's Internal Technical Conference 2019, 2019 | | 2019 |
| Efficient and Portable Full Chip Clock Distribution Methodology for SoC Designs J Chetia, K Pokhrel, N Bindlish Intel's Internal Technical Conference 2017, 2017 | | 2017 |
Bharat BhuvaVanderbilt University在 vanderbilt.edu 的电子邮件经过验证
