| A 60-GHz 16qam/8psk/qpsk/bpsk direct-conversion transceiver for ieee802. 15.3 c K Okada, N Li, K Matsushita, K Bunsen, R Murakami, A Musa, T Sato, ... IEEE Journal of Solid-State Circuits 46 (12), 2988-3004, 2011 | 336 | 2011 |
| 64-QAM 60-GHz CMOS transceivers for IEEE 802.11 ad/ay R Wu, R Minami, Y Tsukui, S Kawai, Y Seo, S Sato, K Kimura, S Kondo, ... IEEE Journal of Solid-State Circuits 52 (11), 2871-2891, 2017 | 196* | 2017 |
| A 28-GHz CMOS phased-array transceiver based on LO phase-shifting architecture with gain invariant phase tuning for 5G new radio J Pang, R Wu, Y Wang, M Dome, H Kato, H Huang, AT Narayanan, H Liu, ... IEEE Journal of Solid-State Circuits 54 (5), 1228-1242, 2019 | 185 | 2019 |
| Full four-channel 6.3-Gb/s 60-GHz CMOS transceiver with low-power analog and digital baseband circuitry K Okada, K Kondou, M Miyahara, M Shinagawa, H Asada, R Minami, ... IEEE Journal of Solid-State Circuits 48 (1), 46-65, 2012 | 180 | 2012 |
| A 39-GHz 64-element phased-array transceiver with built-in phase and amplitude calibrations for large-array 5G NR in 65-nm CMOS Y Wang, R Wu, J Pang, D You, AA Fadila, R Saengchan, X Fu, ... IEEE Journal of Solid-State Circuits 55 (5), 1249-1269, 2020 | 171 | 2020 |
| A 28-GHz CMOS phased-array beamformer utilizing neutralized bi-directional technique supporting dual-polarized MIMO for 5G NR J Pang, Z Li, R Kubozoe, X Luo, R Wu, Y Wang, D You, AA Fadila, ... IEEE Journal of Solid-State Circuits 55 (9), 2371-2386, 2020 | 168 | 2020 |
| A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ... IEEE Journal of Solid-State Circuits 50 (1), 68-80, 2014 | 158 | 2014 |
| A low phase noise quadrature injection locked frequency synthesizer for mm-wave applications A Musa, R Murakami, T Sato, W Chaivipas, K Okada, A Matsuzawa IEEE Journal of Solid-State Circuits 46 (11), 2635-2649, 2011 | 147 | 2011 |
| Class-C VCO with amplitude feedback loop for robust start-up and enhanced oscillation swing W Deng, K Okada, A Matsuzawa IEEE Journal of Solid-State Circuits 48 (2), 429-440, 2012 | 139* | 2012 |
| A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB AT Narayanan, M Katsuragi, K Kimura, S Kondo, KK Tokgoz, K Nakata, ... IEEE Journal of Solid-State Circuits 51 (7), 1630-1640, 2016 | 132 | 2016 |
| 20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding K Okada, R Minami, Y Tsukui, S Kawai, Y Seo, S Sato, S Kondo, T Ueno, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 131 | 2014 |
| A compact, low-power and low-jitter dual-loop injection locked PLL using all-digital PVT calibration A Musa, W Deng, T Siriburanon, M Miyahara, K Okada, A Matsuzawa IEEE Journal of Solid-State Circuits 49 (1), 50-60, 2013 | 128 | 2013 |
| 300-GHz. 100-Gb/s InP-HEMT wireless transceiver using a 300-GHz fundamental mixer H Hamada, T Fujimura, I Abdo, K Okada, HJ Song, H Sugiyama, ... 2018 IEEE/MTT-S International Microwave Symposium-IMS, 1480-1483, 2018 | 125 | 2018 |
| A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver KK Tokgoz, S Maki, J Pang, N Nagashima, I Abdo, S Kawai, T Fujimura, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 168-170, 2018 | 123 | 2018 |
| A full 4-channel 6.3 Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry K Okada, K Kondou, M Miyahara, M Shinagawa, H Asada, R Minami, ... 2012 IEEE International Solid-State Circuits Conference, 218-220, 2012 | 122 | 2012 |
| 300-GHz-band 120-Gb/s wireless front-end based on InP-HEMT PAs and mixers H Hamada, T Tsutsumi, H Matsuzaki, T Fujimura, I Abdo, A Shirane, ... IEEE Journal of Solid-State Circuits 55 (9), 2316-2335, 2020 | 121 | 2020 |
| A 50.1-Gb/s 60-GHz CMOS transceiver for IEEE 802.11 ay with calibration of LO feedthrough and I/Q imbalance J Pang, S Maki, S Kawai, N Nagashima, Y Seo, M Dome, H Kato, ... IEEE Journal of Solid-State Circuits 54 (5), 1375-1390, 2019 | 116* | 2019 |
| A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11 ad T Siriburanon, S Kondo, M Katsuragi, H Liu, K Kimura, W Deng, K Okada, ... IEEE Journal of Solid-State Circuits 51 (5), 1246-1260, 2016 | 107 | 2016 |
| A 60GHz CMOS power amplifier using capacitive cross-coupling neutralization with 16% PAE H Asada, K Matsushita, K Bunsen, K Okada, A Matsuzawa 2011 41st European Microwave Conference, 1115-1118, 2011 | 97 | 2011 |
| A 0.114-mW dual-conduction class-C CMOS VCO with 0.2-V power supply K Okada, Y Nomiyama, R Murakami, A Matsuzawa 2009 Symposium on VLSI Circuits, 228-229, 2009 | 93 | 2009 |
Atsushi ShiraneTokyo Institute of Technology在 m.titech.ac.jp 的电子邮件经过验证
